Contributors to all versions of the spec in alphabetical order

  • Allen Baum

  • Jordan Carlin

  • James Kaden Cassidy

  • David Harris

  • Georgia Tai

  • Mike Thompson

This document is released under a Creative Commons Attribution 4.0 International License.

This Certification Test Plan (CTP) is a work in progress. It describes the coverpoints and tests being developed by the RISC-V Certification Steering Committee. It is intended to be read in conjunction with the Certification Requirements Documents (CRDs) defining the features in each certificate, and the riscv-arch-test repository that contains information about how to use and contribute to the tests.

1. Introduction

This Certification Test Plan describes the coverpoints and tests to certify RISC-V profiles. It summarizes the profiles intended to be supported and the test suites that need to run on each profile. It also summarizes the contents of each test suite. This CTP will also include coverpoints and tests for features that are not part of a certified profile.

1.1. Certificates and Certification

A RISC-V Certificate is a named set of requirements for a RISC-V implementation, typically defined by a ratified profile and a set of additional requirements. For example, the RVA23 Certificate requires meeting the RVA23S64 profile and having a conforming machine mode implementation.

Certification is the process of testing that a RISC-V implementation meets the requirements of a RISC-V certificate. The goal of certification is to deliver software interoperability across implementations.

There is a fuzzy line between certification and verification. Certification involves testing that an implementation meets all of the normative rules in ratified specifications relevant to the certificate, but does not involve testing that requires detailed knowledge of the microarchitecture. Specifically, certification does not check timing (such as the arrival of interrupts relative to the start, middle, or end of multicycle instructions), pipeline hazards, power management features, etc.

Certification assumes the ratified specification is read and interpreted with knowledge of computer architecture and reasonable judgement, because not every detail is spelled out in normative rules. For example, certification that "ADD performs the addition of rs1 and rs2" involves testing ADD with a reasonable set of values. The test plan author exercises judgement selecting these values because they are not spelled out. For example, the values might involve every combination of {0, 1, -1, maximum positive integer, maximum negative integer, intermediate value} for the two source register values. The intermediate value involves an arbitrary choice. A reasonable author might pick some other sensible edge values, such as some values one more or less than those in the set above. However, certification does not attempt to prove every bit of a carry chain works for every possible input, or that all stuck-at faults would be detected. Similarly, the test plan author may exercise all 32 registers as sources or destinations for each instruction, which is implicitly required but not spelled out in a normative rule.

When in doubt, it is better to test slightly more than strictly necessary for normative rules, rather than slightly less. Over-testing is acceptable, as long as it does not cause false failures or excessive test time. It is often easier to test cross-products of all relevant inputs, even if not all combinations are explicitly named by normative rules. It also reduces the risk of human error missing a required combination.

An implementation that passes certification tests is said to be certified for the relevant certificate. The process of certification is described in TODO CSC page.

1.2. Normative Rules, Coverpoints, and Tests

Normative rules are the key to certification. They are the features of the RISC-V architecture that need to be tested in order to certify a profile. However, normative rules are human-readable portions of a specification and cannot be checked in an automated manner.

Instead, certification relies on coverpoints, which are machine-readable descriptions of the features to be tested. Every normative rule is tied to one or more coverpoints, such that if the coverpoints are hit, the normative rule is considered to be certified.

Each coverpoint has a set of tests that exercise it, and each test has a set of coverpoints that it hits.

This test plan defines the normative rules that must be hit for each profile, specifies the coverpoints that measure those rules, and outlines the tests that hit those coverpoints. The tests are self-checking, and report pass/fail results. The coverage report confirms that the tests hit all the coverpoints and thus all the normative rules.

Coverpoints are written in SystemVerilog, and are designed to be used with the Extended RISC-V Verification Interface (RVVI). They are written to be independent of the DUT (Device Under Test), so that they can be used with any RISC-V implementation. [1] Functional coverage is collected using SystemVerilog infrastructure adapted from riscvISACOV [2].

Coverpoints are organized into .svh SystemVerilog coverage files, each of which contain one or more covergroups, each of which contain one or more coverpoints. Coverage files apply to a DUT with a particular set of extensions. For example, the I_coverage.svh coverage file is used for any 32 or 64-bit DUT that supports the I extension. The ZfhD.svh coverage file applies to a DUT that supports both the Zfh and D extensions (and includes conversions between half and double-precision, which do not exist if Zfh or D alone are implemented).

Tests are written in assembly language .S files. Tests are organized into directories for each extension, and into a privileged directory. The coverpoints are hit by running all of the applicable tests in a directory. For example, RV32I coverage involves running add.S, addi.S, sub.S, etc. RV64I coverage also involves running addw.S, which is unique to RV64.

1.3. Glossary

The following terms are used in this test plan:

  • Extensions: named and ratified RISC-V extensions, such as RV32I, M, Zbb, Zicsr, or Svadu. Many extensions define instructions or CSRs, but some only define parameters (e.g. Sstvecd requires that the STVEC_MODE_DIRECT=True).

  • Parameters: options describing the behavior of extensions. All parameters will be named by the Parameters Working Group (started February 2026) and will appear in UDB. For example, the PMP_GRANULARITY parameter defines the minimum size of a PMP region.

  • Configuration: A set of extensions and parameters partially or fully describing the behavior of a RISC-V hart. A full configuration is sufficient for a reference model to exactly match the behavior of a DUT except with regard to non-deterministic behaviors. Configurations are described in machine-readable YAML format that are read by UDB and used to generate configuration files for various tools.

  • Constrained Non-Deterministic Behaviors: behaviors that cannot be predicted based on either architectural configuration or defined parameters, but whose result are constrained to be a small number of possible values. The example of a tail-agnostic vector instruction is one of those, where the number of legal results is limited to just two: either the previous value, or all ones. Either behavior is correct, and the hart might change behaviors from one instruction to the next, so the DUT and reference model cannot be guaranteed to exactly match. Self-checking tests must accept all legal outcomes for non-deterministic behaviors.

  • Unconstrained Non-Deterministic Behaviors: behaviors that cannot be predicted based on either architectural configuration or defined parameters, and whose result is not constrained to a small number of possible values. For example, the value of an integer register after reset is an unconstrained non-deterministic behavior. Tests must not make any assumptions about the value of such behaviors, and must not check them against the reference model.

  • Profile: A named collection of required and optional extensions, such as RVI20 or RVA23S64. Profiles may be ratified by RISC-V or developed by the Certification Steering Committee to meet certification market needs, such as a simple microcontroller. A profile is a partial configuration. The test plan must allow the DUT configuration to indicate which optional extensions and other parameters are used, and fully test all optional profile extensions provided by the DUT.

  • UDB: Unified Database, a standardized way to describe the configuration and generate config files for various tools from a single point of truth.

  • Normative rule: Description of a single certifiable feature, preferably a direct quotation from a ratified specification.

  • Coverage files: a SystemVerilog .svh file containing all of the covergroups for an extension or combination of extensions, such as I_coverage.svh or ZfaD_coverage.svh.

  • Covergroup: A SystemVerilog construct that contains one or more coverpoints. Covergroups are used to collect functional coverage of a particular feature or set of features in the RISC-V architecture. For example, the I_coverage.svh file contains a covergroup for each instruction in the I extension, such as add, addi, sub, etc. The InterruptsSm_coverage.svh contains a single InterruptsSm_cg covergroup with all the coverpoints for machine-mode interrupts.

  • Coverpoint: A SystemVerilog construct describing a set of conditions to test. For example, the cp_rd coverpoint checks that all 32 destination registers x0-x31 are exercised by instructions that don’t trap. Each coverpoint has one or more bins; for example, cp_rd has 32 bins for the different registers.

  • Bin: One target value for a coverpoint. Each bin may be covered or not by a test suite.

  • Test files: A file containing one or more tests, typically written in assembly language. For example, rv32/I/add.S contains all of the RV32 tests to exercise the add_cg covergroup in I_coverage.svh.

  • Test: A snippet of code, typically a sequence of assembly language instructions, that exercises at least one bin of a coverpoint.

  • Test Suite: A collection of coverage and test files to test a particular extension, combination of extensions, or group of extensions. For example, the RV32I test suite contains the I_coverage.svh coverage file and the rv32/I/add.S, addi.S, sub.S, and other tests files with tests that hit the coverpoints in that coverage file. The RV64ZfaD test suite contains the ZfaD_coverage.svh coverage file and the rv64/ZfaD/fround.d.S, and other tests files with tests that hit the coverpoints in that coverage file. The RVA23S64 test suite contains all of the required and selected optional test suites for the profile, incluidng RV64I, RV64ZfaD, ExceptionsS, etc.

  • RVMODEL DUT-Specific Macros: A set of macros that perform semihosting/trick box functions such as booting the DUT, sending interrupts, and logging results. The macros are defined in RVMODEL DUT-Specific Macros.

Beware that Test Suite is also used outside this document to mean a full set of tests for a given profile from a given provider. For example, Synopsys, Breker, and riscv-arch-test all have test suites for the RVI20U32 profile.

2. Certification Process

Certifying a RISC-V Device-Under-Test (DUT) involves the following steps:

  • Selecting a profile for the DUT

  • Providing a Unified Database (UDB) configuration for the DUT, such as optional extensions, peripheral addresses, and PMP granularity

  • Generating self-checking tests based on the selected profile and UDB

  • Running the tests and reporting pass/fail

Test developers also need to

  • Generate a coverage report confirming that the tests hit all the coverpoints based on a Sail trace

TODO: Update to point to CSC page when ready.

3. Profiles & Test Suites

This test plan addresses Phase 0, Phase 1, and Phase 2 RISC-V certification objectives, including the following ratified and unratified profiles. The following is a summary of the Certification Requirement Documents (CRDs) for each phase, and changes to the CRDs supersede anything in this summary.

  • RVI20 Profile (Ratified): Phase 0

    • RV{32/64}IMAFDC_Zifencei_Zicntr_Zihpm with no Sm machine mode, no PMP. Zicsr instructions only access counters and floating-point CSRs. Optional support for misaligned loads/stores (MISALIGNED_LDST parameter). TODO: Update to point to CRD when ready.

  • MC100 Microcontroller Profile (MC100-32-CRD.pdf): Phase 1

    • RV{32/64}IMZca_Zifencei_Zicsr_Zicntr with machine mode 1.11, counters, exceptions, interrupts, PMP16

  • RVA22S64 Profile (Ratified): Phase 1.5, stepping stone to phase 2

    • Application processor without vector, hypervisor, and other newer extensions

  • RVB23S64 Profile (Ratified): Phase 1.8, stepping stone to phase 2

    • RVA23 less vector and hypervisor

  • RVA23 Profile (AC200 CRD): Phase 2

Where a CRD is available, it lists the mandatory and optional extensions and IN/OUT-OF_SCOPE parameters. TODO: Update links when CRDs are finalized.

This test plan makes some further assumptions, which should be checked against the CRDs when they become available: * All certificates for profiles that support interrupts (Phase 1 and above) require that the platform be able to set and clear via software all interrupt pending bits defined by the certificate. TODO: Relax this. * Although the RVI20 profile states that ecall causes a trap to the execution environment, it also says that Zicsr instructions are not supported independent of the Zicntr or F instructions, so there is no way to control mtvec and write a trap handler. Therefore ecall is not exercised. * Atomics and fences are much more interesting in a multi-core / multi-master environment. The base test plan just checks that they execute on a single core. TODO: Add multi-master test plan.

3.1. Profile Coverage Matrix

Table 1 summarizes the coverage files applicable to each profile. x indicates a mandatory extension, and o indicates an optional extension. The certification test plan handles all mandatory and optional extensions.

Coverage files with multiple extensions in the name apply when all the extensions are supported; for example, ZfaZfhD is used in a system supporting Zfa, Zfh, and D extensions.

All privileged suites require at least version 1.12 of the privileged specification. Features specific to version 1.13 are tested separately in the Sm1p13 and Ss1p13 suites.

Table 1. Profile Coverage Files
Coverage File Description Test Plan RVI20 MC100 RVA22S64 RVB23S64 RVA23S64

XLEN

32/64

32

64

64

64

Unprivileged

I

Integer

Table 13

x

x

x

x

x

M

Mult/Div

Table 17

o

x

x

x

x

Zmmul

Mult Only

Table 19

Zaamo

Atomic Memory Ops

Table 36

o

x

x

x

Zalrsc

Load Reserved / Store Cond

Table 38

o

x

x

x

Zca

Compressed

Table 21

o

x

x

x

x

Zcb

Extra Compressed

Table 28

x

x

ZcbM

Compressed Multiply

Table 30

x

x

ZcbZba

Compressed Zero Extend

Table 32

x

x

ZcbZbb

Compressed Sign Extend

Table 34

x

x

Zcf

Compressed Float

Table 24

o

Zcd

Compressed Double

Table 26

o

x

x

x

F

Float

Table 43

o

x

x

x

D

Double

Table 45

o

x

x

x

ZicsrF

Float CSRs

Table 64

o

x

x

x

Misalign

Misaligned Load/Store

Table 83

o

o

o

o

o

MisalignZca

Misaligned Compressed

Table 91

o

o

o

o

o

MisalignF

Misaligned Float

Table 86

o

o

o

o

MisalignD

Misaligned Double

Table 88

o

o

o

o

Zfh

Half

Table 47

o

o

o

ZfhD

Half-Double Converts

[t-ZfhD-coverpoints]

o

o

o

Zfhmin

Half Converts

Table 50

x

o

x

ZfhminD

Half-Double Converts

Table 52

x

o

x

ZfaF

Additional Float

Table 54

x

x

ZfaD

Additional Double

Table 56

x

x

ZfaZfh

Additional Half

Table 58

o

o

ZfaZfhD

Additional Half-Double Converts

Table 60

o

o

Zba

Address Generation

Table 66

x

x

x

Zbb

Basic Bit Manipulation

Table 67

x

x

x

Zbc

Carryless Multiplication

Table 68

o

o

o

Zbs

Single-Bit

Table 69

x

x

x

Zbkb

Bit Manip for Crypto

Table 70

o

Zbkc

Carryless Multiply for Crypto

Table 71

o

Zbkx

Permutations

Table 72

o

Zknd

AES Decryption

Table 74

o

Zkne

AES Encryption

Table 73

o

Zknh

SHA2 Hashing

Table 75

o

Zksed

SM4 Cipher

Table 76

o

Zksh

SM3 Hashing

Table 77

o

Zicsr

CSR Instructions

Table 78

x

x

x

x

Zicond

Conditional Move

Table 95

x

x

Zifencei

Instruction Fence

Table 80

o

x

x

x

x

Zicclsm

Misaligned Loads / Stores

Table 94

o

o

x

x

x

Zihintpause

Pause Hint

Table 104

x

x

x

Zihintntl

Nontemporal Locality Hint

Section A.10.10

x

x

ZihintntlZca

Compressed Nontemporal Locality Hint

Table 106

x

x

Zicbom

Cache Block Flush/Inval

Section A.10.12

x

x

x

Zicboz

Cache Block Zero

Section A.10.13

x

x

x

Zicbop

Cache Block Prefetch

Section A.10.14

x

x

x

Za64rs

Max 64B Reservation Sets

Section A.10.15

x

x

x

Zic64bZicboz

64B Cache Blocks

Section A.11

x

x

x

Privileged

Sm

Machine CSRs

Table 128

x

x

x

x

S

Supervisor CSRs

Table 131

x

x

x

U

User CSRs

Table 133

x

x

x

SmF

Float CSRs

Table 134

o

x

x

x

UF

User Float CSRs

Table 137

x

x

x

Zkr

Entropy CSR

Table 139

o

o

o

ExceptionsSm

Machine Exceptions

Table 140

x

x

x

x

ExceptionsS

Supervisor Exceptions

Table 143

x

x

x

ExceptionsU

User Exceptions

Table 145

x

x

x

ExceptionsF

Float Exceptions

Table 147

x

x

x

ExceptionsZalrsc

LR/SC Exceptions

Table 151

x

x

x

ExceptionsZaamo

AMO Exceptions

Table 152

x

x

x

ExceptionsZc

Compressed Exceptions

Table 153

x

x

x

x

ExceptionsZicboS

Supervisor CBO Exceptions

Table 155

x

x

x

ExceptionsZicboU

User CBO Exceptions

Table 156

x

x

x

ExceptionsSv

Virt Mem Exceptions

Table 157

x

x

x

ExceptionsSvZalrsc

Virt Mem LR/SC Exceptions

Table 158

x

x

x

ExceptionsSvZaamo

Virt Mem AMO Exceptions

Table 159

x

x

x

InterruptsSm

Machine Interrupts

Table 160

x

x

x

x

InterruptsS

Supervisor Interrupts

Table 163

x

x

x

InterruptsU

User Interrupts

Table 166

x

x

x

InterruptsSstc

Supervisor Timer Compare

Table 168

x

x

x

ZicntrS

Supervisor Counters

Table 170

x

x

x

ZicntrU

User Counters

Table 171

x

x

x

Zihpm

Hardware Performance Monitors

Table 101

o

x

x

x

x

EndianSm

Machine Endian

Table 172

EndianS

Supervisor Endian

Table 173

EndianU

User Endian

Table 174

EndianZaamo

AMO Endian

Table 175

EndianZalrsc

LR/SC Endian

Table 176

EndianF

Float Endian

Table 177

EndianZca

Compressed Endian

Table 178

PMPSm

Machine PMP

Table 181

x

x

x

x

PMPS

Supervisor PMP

Table 182

x

x

x

PMPU

User PMP

Table 183

x

x

x

PMPF

Float PMP

Table 184

x

x

x

PMPZca

Compressed PMP

Table 185

x

x

x

x

PMPZicbo

PMP + CBOM/CBOZ

Table 186

x

x

x

PMPZaamo

AMO PMP

Table 187

x

x

x

PMPZalrsc

LR/SC PMP

Table 188

x

x

x

Svbare

No Virtual Memory

Section B.8.2

x

x

x

Sv

Sv32/39/48/57 Virtual Memory

Table 189

x

x

x

Svinval

TLB Invalidation

Table 194

x

x

x

SvPMP

VM + PMP

Table 191

x

x

x

SvZicbo

VM + CBOM/CBOZ

Table 192

x

x

x

SvPMPZicbo

VM + PMP + CBOM/CBOZ

Table 193

x

x

x

Svade

Page Table A/D Exceptions

Table 195

x

x

x

Svadu

Page Table Update

Table 196

o

o

SvaduPMP

Page Table Update + PMP

Table 197

o

o

Svpbmt

Page-based Memory Types

Table 198

x

x

x

Svnapot

Naturally Aligned Pages

Table 199

o

x

x

Sscofpmf

Counter Filtering

Section B.10.2

o

x

x

Ssstateen

Supervisor State Enable

Section B.10.3

o

x

Ssu64xl

64-bit UXL

Section B.10.4

o

x

x

Sscounterenw

Counter Enables Writable

Section B.10.5

x

x

x

Sstvecd

Direct Vector

Section B.10.6

x

x

x

Sstvala

stval Addresses

Section B.10.7

x

x

x

Strict

SsstrictSm

Machine Strict (unratified)

Section B.6.1

o

o

o

SsstrictS

Supervisor Strict

Section B.6.2

o

o

o

Vector

Vx8

Vector Integer 8-bit

Table 108

o

o

x

Vx16

Vector Integer 16-bit

Table 108

o

o

x

Vx32

Vector Integer 32-bit

Table 108

o

o

x

Vx64

Vector Integer 64-bit

Table 108

o

o

x

Vls8

Vector Load/Store 8-bit

Table 109

o

o

x

Vls16

Vector Load/Store 16-bit

Table 109

o

o

x

Vls32

Vector Load/Store 32-bit

Table 109

o

o

x

Vls64

Vector Load/Store 64-bit

Table 109

o

o

x

Vf16 (Zvfh)

Vector Float 16-bit

Table 110

o

o

Vf32

Vector Float 32-bit

Table 110

o

o

x

Vf64

Vector Float 64-bit

Table 110

o

o

x

Zvfhmin

Vector half conversions

Table 111

o

o

Zvfbfmin

Vector BF16 Convert

Table 115

o

o

Zvfbfwma

Vector BF16 MAC

Table 117

o

o

ZfaZvfh

fli for Vector Half

Table 113

o

o

Zvbb8

Vector Bit Manip 8-bit

Section A.12.2

o

x

Zvbb16

Vector Bit Manip 16-bit

Section A.12.2

o

x

Zvbb32

Vector Bit Manip 32-bit

Section A.12.2

o

x

Zvbb64

Vector Bit Manip 64-bit

Section A.12.2

o

x

Zvkb8

Vector Crypto Bit Manip 8-bit

Section A.13.2

o

o

Zvkb16

Vector Crypto Bit Manip 16-bit

Section A.13.2

o

o

Zvkb32

Vector Crypto Bit Manip 32-bit

Section A.13.2

o

o

Zvkb64

Vector Crypto Bit Manip 64-bit

Section A.13.2

o

o

Zvbc64

Vector Carryless Mult

Section A.13

o

o

Zvkg32

Vector GCM

Section A.13.3

o

o

Zvkned32

Vector Crypt

Section A.13.4

o

o

Zvknha32

Vector Hash 32-bit

Section A.13.5

Zvknhb64

Vector Hash 64-bit

Section A.13.5

o

o

Zvksed32

Vector ShangMi Crypt

Section A.13.6

o

o

Zvksh32

Vector ShangMi Hash

Section A.14

o

o

Vector Privileged

ExceptionsVx

Vector Integer Exceptions

Table 148

o

o

x

ExceptionsVf

Vector Float Exceptions

Table 149

o

o

x

ExceptionsVls

Vector Load/Store Exceptions

Table 150

o

o

x

SmV

Vector CSRs

Table 135

o

o

x

SmVF

Vector FP CSRs

Table 136

o

o

x

UV

User Vector CSRs

Table 138

o

o

x

SsstrictV

Vector Strict

SsstrictV Coverpoints

o

o

o

Hypervisor

H

Hypervisor Instructions

Table 200

o

o

x

ExceptionsH

Hypervisor Exceptions

Table 201

o

o

x

ExceptionsHV

Hypervisor Vector Exceptions

Table 202

o

o

x

InterruptsH

Hypervisor Interrupts

Table 203

o

o

x

EndianH

Hypervisor Endian

Table 205

ZicntrH

Hypervisor Counters

Table 206

o

o

x

HV

Hypervisor + Vector CSRs

Table 204

o

o

x

PMPH

Hypervisor PMP

Table 207

o

o

x

SvH

Hypervisor Virtual Memory

Table 208

o

o

x

SvHZicbo

Hypervisor Virtual Memory + CBO

Table 209

o

o

x

Shcounterenw

Counter Enables

Table 210

o

o

x

Shvsatpa

VM Modes Supported

Table 211

o

o

x

Shgatpa

VM x4 Modes Supported

Table 212

o

o

x

Shvstvecd

Direct Vectoring

Table 213

o

o

x

Shvstvala

vstval Addresses

Table 214

o

o

x

Shtvala

htval Addresses

Table 215

o

o

x

Shlcofideleg

Counter Overflow Delegation

Table 216

o

o

x

ZkrH

Hypervisor Entropy

Table 217

o

o

x

SstcH

Hypervisor Supervisor Timer

Table 218

o

o

x

SsstateenH

Hypervisor State Enable

Table 219

o

o

x

SvinvalH

Hypervisor TLB Inval

Table 223

o

o

x

SvaduH

Hypervisor TLB Update

Table 224

o

o

o

ZicfilpH

Hypervisor Landing Pad

Table 225

o

o

o

ZicfissH

Hypervisor Shadow Stack

Table 226

o

o

o

Miscellaneous RV{A/B}23 Extensions

Ss1p13

Supervisor 1p13

Section B.10.8

x

x

Ssnpm

Pointer Masking

Section B.10.9

x

x

SsnpmH

Hypervisor Pointer Masking

Table 228

Zacas

Atomic Compare-And-Swap

Table 119

o

o

Zabha

Subword Atomics

Table 121

o

o

ZacasZabha

Subword CAS

Table 123

o

o

Zama16b

Main memory PMA supports misaligned atomics within 16-byte regions

Table 152

x

Zicfilp

Landing Pads

Section B.10.12

o

o

Zicfiss

Shadow Stack

Section B.10.13

o

o

Zfbfmin

BF16 Convert

Table 62

o

o

Zimop

Maybe-Ops

Section A.14.5

x

x

Zcmop

Compressed Maybe-Ops

Section A.15

x

x

Zawrs

Wait on Reservation Set

Section B.10.14

x

x

Sdtrig

Debug Triggers

Sdtrig Coverpoints

o

o

Non-Profile Extensions

E

Embedded 16 Regs

Table 127

Zfinx

Float in Int Regs

Section A.15.2

Zdinx

Double in Int Regs

Section A.15.3

Zhinx

Half in Int Regs

Section A.15.4

Zhinxmin

Half Cvt in Int Regs

Section A.15.5

Q

Quad-Precision Float

Section A.15.6

ZfhQ

Half-Quad Converts

Section A.15.7

ZfhminQ

Half-Quad Converts

Section A.15.7

ZfaQ

Additional Quad

Section A.15.9

ZfaZfhQ

Additional Half-Quad Converts

Section A.15.10

MisalignQ

Misaligned Quad

[t-MisalignQ-coverpoints]

Zcmp

Compressed Push/Pop

[t-Zcmp-coverpoints]

Zcmt

Compressed Table Jumps

[t-Zcmt-coverpoints]

Zilsd

Load/Store Double

Section A.15.13

Zclsd

Compressed Load/Store Double

Section A.16

Smcsrind

Machine Indirect CSRs

Section B.11.4

Sscsrind

Supervisor Indirect CSRs

Section B.11.5

SscrindH

Hypervisor Indirect CSR

Table 220

o

o

x

Smepmp

Enhanced PMP

Section B.11.6

Smrnmi

Machine Resumable Interrupts

Section B.11.7

Ssrnmi

Supervisor Resumable Interrupts

Section B.11.8

Sm1p13

Machine 1p13

Section B.11.2

x

x

Smstateen

Machine State Enable

Section B.11.3

Smcntrpmf

Cycle and Instret Mode Filtering

Section B.11.9

Smcdeleg

Counter Delegation

Section B.11.10

Ssccfg

Counter Delegation

Section B.11.11

SscfgH

Hypervisor Counter Delegation

Table 221

Smdbltrp

Machine Double Trap

Section B.11.12

Ssdbltrp

Supervisor Double Trap

Section B.11.13

SsdbltrpH

Hypervisor Double Trap

Table 227

Smnpm

Pointer Masking

Section B.10.10

Smmpm

Pointer Masking

Section B.10.11

SmnpmH

Hypervisor Pointer Masking

Table 229

Smctr

Control Transfer Records

Section B.11.14

SmctrH

Hypervisor Control Transfer Records

Table 222

Ssqosid

Quality-of-Service ID

Ssqosid Coverpoints

Debug

DM

Debug Module

[t-DM-coverpoints]

DTM

Debug Transport Module

[t-DTM-coverpoints]

Sdext

Debug Mode

[t-Sdext-coverpoints]

Advanced Interrupt Architecture

Smaia

Machine Advanced Interrupts

Section C.2.2

Ssaia

Supervisor Advanced Interrupts

Section C.2.3

IMSIC

Incoming MSI Controller

Section C.2.4

APLIC

Advanced Platform-Level Interrupt Controller

Section C.3

I/O Memory Management Unit

IOMMU

I/O Memory Management Unit

IOMMU Coverpoints

3.2. Out-of-Scope Extensions

Table 2 lists certain extensions whose behavior is presently outside the scope of certification. An x in the table means the extension is required for that profile. Some of these behaviors are not readily visible at the architectural level of observed program behavior, such as constant-time instructions. PMA properties are implicitly tested by executing instructions that depend on the property, but not tested comprehensively across the entire memory map. Entropy generation requires statistical analysis beyond the present scope of certification. These extensions might be added to scope in the future.

Table 2. Extensions Lacking Architectural Visibility for Certification Testing
Coverage File Description RVI20 uController RVA22S64 RVB23S64 RVA23S64

Ziccif

Main memory PMA supports instruction fetch

x

x

x

Ziccrse

Main memory PMA supports RsrvEventual

x

x

x

Ziccamoa

Main memory PMA supports atomics

x

x

x

Ziccamoc

Main memory PMA supports AMOCASQ

x

x

Zkt

Constant-time scalar crypto

x

x

x

Zvkt

Constant-time vector crypto

x

x

x

Svvptc

Valid PTEs appear within bounded time without fence

x

x

Furthermore, the following features are not supported in this version of the certification test plan:

  • sfence.vma, sinval, and hypervisor fences are lightly tested because it is hard to prove they don’t work

  • Physical Memory Attributes (PMA): no standard representation yet; tests assume programs run in main memory with full capabilities. TODO: Add a mechanism to define memory region PMAs in UDB, and exercise each type of access (load/store/execute, misaligned, at start/middle/end/partially wrapping) to each region.

  • Testing privilege modes whose XLEN differs from MXLEN; low ROI

  • Testing extensions that have been disabled with misa fields; behavior is unspecified.

  • Non-Maskable Interrupts (NMI) - no standard way to generate them yet

  • Reset behavior - no way for a program to reset itself

  • Delegation of MEI/MTI/MSI to S-mode - "most platforms will choose not to make these interrupts delegatable from M-mode to S-mode"

  • Multicore or multi-master systems; current tests only run on one core and atomics and memory consistency are only lightly tested. TODO: coming later.

  • Custom extensions

A hart with these features can still be certified if it meets all other requirements; these features are simply not tested.

TODO: ** which of the Zicc extensions are tested by regular instructions?

3.3. Certification Requirements

Certification places basic requirements on the DUT.

TODO: These should move to the CRD when it is ready.

3.3.1. Conforming M-Mode

The privileged testplan relies on a machine mode conforming to Sm1p12 machine architecture or later. (See also, the privileged spec, "All hardware implementations must provide M-mode".) The tests need to configure machine-mode CSRs that affect the behavior of lower privilege modes. This is done most easily by directly writing such registers using standard instructions in machine mode. It is theoretically possible to write tests that only operate in S and U-mode, and use some sort of generalized SBI interface to request machine mode configurations even from non-conforming machine-mode implementations, but no such SBI interface exists at this time and the complexity seems to exceed the benefit. Therefore, privileged tests rely on machine-mode, and also contain coverpoints and tests to check that privileged behaviors work correctly in machine mode.

3.3.2. Consistent XLEN and Endianness

The test plan requires that after the boot process, XLEN and endianness are the same in all privilege modes. Specifically, MXLEN = SXLEN = UXLEN = HSXLEN = VSXLEN and MBE = SBE = UBE = VSBE. If this is not the reset state of the DUT, the RVMODEL_BOOT macro may be able to place it in that state before testing. If the DUT cannot be placed in this state, it cannot be certified because the tests assume XLEN and endianness do not change with privilege mode unless specifcially modified by a test. For example, a machine hardwired to 64-bit machine mode and 32-bit user mode is not certifiable. (Presently, only endian changes are tested; certifying multiple XLEN is not a priority.)

4. General Test Plan Strategy

This CTP describes tests for all supported RISC-V profiles, but the tests run on a specific DUT. The DUT memory map is defined by a Linker Script. The DUT configuration is described with RISC-V Unified Database, and supplementary files such as simulator configuration files are (TODO) automatically generated from the UDB so there is a single configuration file to maintain. The UDB describes the supported extensions, and also has parameters defining optional behaviors of those extensions. If a behavior is UNSPECIFIED in the specification, it is not tested because there are no wrong answers. A common purpose of parameters is to define the behavior of WARL fields in CSRs.

4.1. Configuration

The DUT is described with a Unified Database (UDB) YAML file. This file lists:

  • all of the supported extensions

  • all of the parameters required to describe the behavior of the extensions

The DUT also needs to know how to boot the core, terminate a test with a success code, send a message to a console, and cause interrupts. These DUT-specific behaviors are defined by RVMODEL DUT-Specific Macros, which are an assembly-language library implementing an API using DUT-specific hardware.

4.2. Unified Database

Unified Database allows partially- and fully-configured descriptions. A profile is an example of a partially configured description because it has a mix of required and optional extensions, and does not specify parameter values for most of the extensions. A DUT needs to have a fully configured description including precisely which versions of which extensions are supported and what parameter values are implemented, so that a simulator can exactly match its behavior.

The certification framework requires a fully-configured UDB description of the DUT and RVMODEL macros for the DUT. It uses UDB to produce supplementary configuration files including:

  • Sail JSON file configuring reference model to match DUT

  • Configuration files for other optional simulators, such as Spike, ImperasFPM

  • SystemVerilog coverage.svh file describing which coverage files and parameter values to use for coverage measurement

  • Optional DUT configuration files (CORE-V Wally Example) providing parameter values to configurable RTL

4.2.1. Configuration Parameters

The UDB parameters for each extension are defined in:

github.com/riscv/riscv-unified-db/tree/main/spec/std/isa/ext riscv.github.io/riscv-unified-db/index.html

  • The CSC Tests and Models working group developed the following list of configuration parameters. Need to check if they match the parameters in UDB extensions.

docs.google.com/spreadsheets/d/1tFGLbocTp1YNn11aN8JTmvxL_23e7x8SlBNJfOPRmAE/edit?gid=0#gid=0

A partially-configured UDB description of each profile is given in:

4.3. Unspecified and Reserved Behaviors

Some RISC-V behaviors are UNSPECIFIED, which means an implementation can do anything. These behaviors are not tested because there is no wrong answer. Table 3 summarizes the normative rules regarding reserved behaviors.

Unimplemented opcodes (except in the custom space) and instructions accessing non-existent CSRs are reserved. The behavior of reserved instructions is UNSPECIFIED, so they should not be tested by most testplans. However, when the Ssstrict extension is enabled, reserved instructions raise an illegal instruction exception. This is tested by the SsstrictS test plan.

Ssstrict states that the illegal instruction is contained in the supervisor-mode trap handler. Certification tests do not exercise the execution environment, so the illegal instruction traps to machine mode.
Table 3. I Normative Rules Regarding Behaviors
Spec Section Normative Rule

Unpriv 1.7

The term UNSPECIFIED refers to a behavior or value that is intentionally unconstrained.

Unpriv 2.2

For this purpose, we divide each RISC-V instruction-set encoding space (and related encoding spaces such as the CSRs) into three disjoint categories: standard, reserved, and custom. …​ Reserved encodings are currently not defined but are saved for future standard extensions; once thus used, they become standard encodings. …​ The behavior upon decoding a reserved instruction is UNSPECIFIED.

Privileged 2.1

Instructions that access a non-existent CSR are reserved.

rva23-profile

Ssstrict No non-conforming extensions are present. Attempts to execute unimplemented opcodes or access unimplemented CSRs in the standard or reserved encoding spaces raises an illegal instruction exception that results in a contained trap to the supervisor-mode trap handler.

TODO: Generate this table from norm rules via YAML when Ssstrict is tagged.

4.4. CSR Bitfields

CSR fields can be Write Preserves, Read Ignores (WPRI), Write Legal, Read Legal (WLRL), or Write Any, Read Legal (WARL). Examples of WPRI fields include undefined fields of xstatus, xenvcfg, mseccfg, and xstateen* that could have unintended side effects if they are subsequently defined and unwittingly set to nonzero values. Examples of WLRL fields include xcause.ExceptionCode and hstatus.VGEIN. Other CSR fields are generally WARL.

WPRI fields are not tested. WLRL fields are tested with all legal values but no illegal values. WARL fields are tested by trying all possible values of the field. CSR tests ([Zicsr]) for WARL fields generally involve setting all bits to 1, setting all to 0, and writing walking 1s. Therefore, they inherently exercise all possible values of 1 and 2-bit WARL fields. Longer fields can be tested exhaustively if the number of possibilities is small (such as satp.MODE), or just with walking 1s if the number of possibilities is too large (such as misa.EXTENSIONS).

TODO: reconcile this with CRD that illegal values are not supported for WARL fields. Parameters are needed to specify the illegal values for a DUT. The reference model could read these parameters, and then the tests could exercise all values and match the reference model. Should there be discretion about what to do? riscv.github.io/riscv-unified-db/pdfs/RVI20-32-CRD.pdf

Table 4 summarizes the normative rules regarding CSR bitfields.

Table 4. I Normative Rules Regarding Bitfields
Spec Section Normative Rule

Privileged 2.3

Some whole read/write fields are reserved for future use. Software should ignore the values read from these fields, and should preserve the values held in these fields when writing values to other fields of the same register. For forward compatibility, implementations that do not furnish these fields must make them read-only zero. These fields are labeled WPRI in the register descriptions.

Privileged 2.3

Some read/write CSR fields specify behavior for only a subset of possible bit encodings, with other bit encodings reserved. Software should not write anything other than legal values to such a field, and should not assume a read will return a legal value unless the last write was of a legal value, or the register has not been written since another operation (e.g., reset) set the register to a legal value. These fields are labeled WLRL in the register descriptions.

Privileged 2.3

Implementations are permitted but not required to raise an illegal-instruction exception if an instruction attempts to write a non-supported value to a WLRL field. Implementations can return arbitrary bit patterns on the read of a WLRL field when the last write was of an illegal value, but the value returned should deterministically depend on the illegal written value and the value of the field prior to the write.

Privileged 2.3

Some read/write CSR fields are only defined for a subset of bit encodings, but allow any value to be written while guaranteeing to return a legal value whenever read. Assuming that writing the CSR has no other side effects, the range of supported values can be determined by attempting to write a desired setting then reading to see if the value was retained. These fields are labeled WARL in the register descriptions.

Privileged 2.3

Implementations will not raise an exception on writes of unsupported values to a WARL field. Implementations can return any legal value on the read of a WARL field when the last write was of an illegal value, but the legal value returned should deterministically depend on the illegal written value and the architectural state of the hart.

TODO: These rules are not yet named and tagged in the spec. Suggest adding them as normative rules.

  • should there be a parameter about WLRL fields throwing illegal instruction when an illegal value is written?

4.5. Normative Rules

The testplan for each extension contains a list of normative rules applicable to that extension. Normative rules are generally direct quotations from a ratified RISC-V specification describing a single certifiable feature. Normative rules specify the behaviors an implementation must meet in order to be compliant with the standard. In particular, introductory overview and non-normative explanatory text is not quoted as a normative rule.

See tagging_normative_rules for more information about normative rules and IDs and how to tag them in the specification.

4.6. Coverpoints

Coverpoints are written with one file that covers both RV32 and RV64, to reduce the duplication and risk of becoming out of sync. When a coverage file contains coverpoints that apply only to one XLEN or the other (e.g. 32 or 64-bit edge values), they are separated by `ifdef XLEN32 or XLEN64 directives. Similarly, when a coverpoint applies only to a certain parameter value (PMP NA4 regions are not supported for granularity coarser than 4 bytes), they uses `ifdef to exclude tests based on the parameter value.

Not all normative rules have coverpoints and tests. A normative rule that a behavior is UNSPECIFIED is not tested because there is no wrong answer. For example, writing satp.MODE = Bare with nonzero values in other fields has unspecified behavior and is untested. The CTP may declare that other normative rules are too difficult to test relative to their value (low return on investment) and choose not to test them. For example, if the Zcf extension is supported, misa.C depends on whether misa.F is supported. misa.F is WARL and may be read-only one, so it is not always possible to test the misa.C dependence on misa.F = 0 and, for simplicity, this dependence might never be tested.

To the extent that there are any normative rules associated with instruction opcodes or CSR numbers, if these rules can be tested by coverpoints that execute the instruction or access the CSR, then no other coverpoints are needed. For example, a normative rule that an add instruction has op = 0110011, funct3 = 000, and funct7 = 0000000 is tested by the ordinary coverpoints that exercise the add instruction.

4.7. Tests

Privileged tests are mostly generated by scripts. They preferably share a single .S file that can be compiled for either RV32 or RV64, again with ifdef directives to separate the two. Unprivileged tests are generated from a template using a Python script, and are divided into RV32 and RV64 directories because the random values differ with XLEN.

5. Test Suite Requirements

The test suites may be provided by multiple suppliers, but must meet a common set of requirements to interoperate transparently for the user:

  • All tests use a common set of DUT configuration files so the user only has to write them once:

    • <dut>.yaml for the UDB configuration including supported extensions and parameter values

    • rvmodel_macros.h for the RVMODEL DUT-Specific Macros

    • link.ld for the linker script

  • All tests are self-checking

    • Able to run on simulators, RTL, and hardware

    • Expected values may be produced by the Sail reference model or the test code itself, and must account for relevant parameters

    • Only test features whose behavior is specified for the given parameters (e.g. only test unimplemented instructions if Ssstrict is supported)

    • Calls RVMODEL_BOOT for DUT-specific boot code before starting the test

    • Terminate with RVMODEL_HALT_PASS or RVMODEL_HALT_FAIL to indicate success

    • Print meaningful information to localize a failure with RVMODEL_IO_WRITE_STR, including:

      • PC at failure point

      • Expected and actual values of mismatching registers

      • Name of coverpoint and bin that failed, if practical

    • Tests should not contain loops over multiple bins. Each bin of each coverpoint should be tested by a unique instruction so that a failing bin can be uniquely identified from the program counter. Loops should go in the test generator instead of the test itself.

  • All tests contain test configuration information (YAML comments) so the framework can identify which ones to run on a DUT

    • List of required extensions and parameter values that the DUT must support to run the test

    • Whether the expected result is configuration-dependent or not (i.e. whether it needs to be regenerated for different configurations or can be run unmodified on any configuration that meets the requirements)

    • Tests are organized in a highly granular way so that each ISA feature can be tested independently of other features

  • All tests are written in assembly or C and work with both GCC and Clang

  • Each test runs on Sail and Spike for at least one choice of parameters

  • Tests are for certification, not verification

    • Every normative rule is addressed by at least one coverpoint, defined in the CTP

    • Every test is directed to a specific coverpoint bin, not fuzzing in the hopes of randomly hitting a coverpoint

    • Tests emphasize RISC-V architectural behavior, not microarchitectural behavior such as complex pipeline hazards or timing

    • Runtime is important

  • All tests have SystemVerilog coverpoints

    • Use standard syntax compatible with Questa, VCS and Xcelium (regression on at least Questa)

  • All testing collateral (tests, test generators, coverpoints, frameworks, documentation, etc.) are owned by RVI and distributed under an open-source license

    • Hosted in the riscv-non-isa/riscv-arch-test GitHub repository under the stewardship of Architectural Certification Test (ACT) SIG

    • Repository contains tests for ratified and in-development features, not just features in certificates

    • Generators necessary to recreate the tests for a DUT are included in the repository, but, when tests are not unique to a DUT, the generated tests themselves are also included to reduce requiring users to run generators and to make the tests easier to view and understand

  • Don’t let the perfect be the enemy of the good

    • If necessary to meet schedule, tests can be released addressing most of the normative rules and coverpoints for a feature, and improved over time

    • Initial test development prioritizes the common parameter choices (such as XLEN=MXLEN, Endian=Little), and other parameter choices can be added over time

    • All limitations must be documented in CTP

5.1. For discussion:

  • Should Sail be the only reference model used for results, so RVI only has to maintain one reference model? Or is support for Whisper also a requirement?

  • Should all coverage be collected via RVVI and SystemVerilog coverpoints, so RVI only has to maintain one coverage flow?

  • Testing of WARL, WLRL, WPRI fields, and the necessary parameters to define what fields should be tested and behaviors should be expected

  • Regression requirements, including multiple parameters

6. RVMODEL DUT-Specific Macros

Each DUT requires implementing a set of macros to perform the following non-ISA functions:

  • Run DUT-specific boot code

  • Terminate a test with a pass or fail indication

  • Send a character to a terminal

  • Deliver each supported type of interrupt to the core (Machine/Supervisor External/Timer/Software + guest external interrupts)

The macro names begin with RVMODEL, so they are called RVMODEL DUT-Specific Macros. Their functions are sometimes called semihosting or trick box.

The RVMODEL DUT-Specific Macros rely on the capabilities of the SoC and/or testbench. For example, a SoC with a 16550-compatible UART sends a character by writing a byte to the UART’s memory-mapped Transmit Holding Register. A SoC without a UART may have a testbench that monitors writes to a specific memory address and prints the byte written to that address.

Most macros are implemented in config/cores/<core>/<version>/rvmodel_macros.h. RVMODEL_ACCESS_FAULT_ADDRESS is defined in rvtest_config.h and rvtest_config.svh for the test programs and coverpoints, respectively.

6.1. Macros

The RVMODEL DUT-Specific Macros are given in Table 5. The Mode column indicates the privilege mode from which the macro is called.

Table 5. RVMODEL DUT-Specific Macros
Macro Description Mode

RVMODEL_BOOT

Perform boot operations, such as turning on a phase-locked loop or DRAM controller or initializing custom state. Cannot clobber x1/ra, but any other registers may be trashed.

Machine

RVMODEL_HALT_PASS

Terminate test with a pass indication. When the test is run in simulation, this should end the simulation.

Any

RVMODEL_HALT_FAIL

Terminate test with a fail indication. When the test is run in simulation, this should end the simulation.

Any

RVMODEL_IO_INIT(_R1, _R2, _R3)

Initialization steps needed prior to writing to the console. _R1, _R2, and _R3 are temporary registers that may be trashed by the macro.

Machine

RVMODEL_IO_WRITE_STR(_R1, _R2, _R3, _STR_PTR)

Write a null-terminated ASCII string to the console, where _R1, _R2, and _R3 are temporary registers that may be trashed by the macro and _STR_PTR is a register containing the address of the first byte of the string.

Any

RVMODEL_SET_MEXT_INT

Sets the Machine External Interrupt mip.MEIP using platform-specific interrupt controller, if supported

Machine or Supervisor

RVMODEL_CLR_MEXT_INT

Clears the Machine External Interrupt mip.MEIP using platform-specific interrupt controller

Machine or Supervisor

RVMODEL_SET_MSW_INT

Sets the Machine Software Interrupt mip.MSIP using a memory-mapped control register, if supported

Machine or Supervisor

RVMODEL_CLR_MSW_INT

Clears the Machine Software Interrupt mip.MSIP using a memory-mapped control register

Machine or Supervisor

RVMODEL_SET_SEXT_INT

Sets the Supervisor External Interrupt sip.SEIP using platform-specific interrupt controller, if supported

Machine or Supervisor

RVMODEL_CLR_SEXT_INT

Clears the Supervisor External Interrupt sip.SEIP using platform-specific interrupt controller

Machine or Supervisor

RVMODEL_SET_SSW_INT

Sets the Supervisor Software Interrupt sip.SSIP using a platform-specific interrupt controller, if supported

Machine or Supervisor

RVMODEL_CLR_SSW_INT

Clears the Supervisor Software Interrupt sip.SSIP by using a platform-specific interrupt controller, as applicable

Machine or Supervisor

RVMODEL_ACCESS_FAULT_ADDRESS

The base address of a region of at least 128 bytes that causes an access fault when any part of the region is read or written. This is used to test exceptions.

n/a

RVMODEL_MTIME_ADDRESS

The address of the memory-mapped mtime register, used for timer accesses and interrupts.

n/a

RVMODEL_MTIMECMP_ADDRESS

The address of the memory-mapped mtimecmp register, used for timer interrupts.

n/a

RVMODEL_DATA_SECTION

Model-specific data that will be placed in a .data section. Used for memory-mapped regions like tohost/fromhost. Macro can be empty if not needed.

n/a
RVMODEL interrupt macros are only required for interrupts controlled in a platform-specific fashion. RISC-V has standardized generating timer interrupts using memory-mapped MTIME and MTIMECMP, so no RVMODEL macros are needed for DUT-specific timer interrupt generation. Similarly, no RVMODEL macros are needed to set or read MTIME, or set or clear interrupts using standard CSR accesses.
If a macro needs machine mode privileges to perform its function but might be called from any mode, it must change privilege level. For example, if RVMODEL_IO_WRITE_STR needs machine mode to access a UART, it may call RVTEST_GOTO_M_MODE. Printing (and halting) is done at the end of a test, so there is no need to return to the previous privilege mode.

6.2. RVMODEL_BOOT Requirements

The RVMODEL_BOOT macro may be empty for a simple DUT.

For a complex SoC, the macro may need to perform initialization steps such as turning on a phase-locked loop or DRAM controller or initializing custom state. It must not clobber x1/ra, but any other registers may be trashed.

At the end of RVMODEL_BOOT, the system should be in conforming machine mode, with XLEN and endianness for each lower privilege mode set to the same value as in machine mode (MXLEN = SXLEN = UXLEN = HSXLEN = VSXLEN and MBE = SBE = UBE = VSBE).

6.3. RVMODEL Macros for Spike and SAIL

RVMODEL macros for Spike are implemented in spike-rv64-max/rvmodel_macros.h. They use HTIF for termination, and write to a virtual UART at address 0x1000_0000 to print characters. TODO: Interrupts

RVMODEL macros for Sail are implemented in tests/env/sail_test.h. They are similar to Spike but use HTIF for printing. TODO: interrupts

6.4. Host Target Interface

The host target interface (HTIF) is an unofficial semihosting method that has become widely used by RISC-V simulators (Spike, QEMU, Sail) and test benches. If your SystemVerilog testbench supports it, you can share the same HTIF code as Spike and Sail for the RVMODEL_HALT_PASS, RVMODEL_HALT_FAIL, and RVMODEL_IO_WRITE_STR DUT-specific macros. A drawback is that your testbench needs to parse the ELF labels to find the address of the tohost symbol, which is used for HTIF communication. If your testbench does not support HTIF, you can implement the RVMODEL macros using other methods, such as memory-mapped I/O to a SoC peripheral or an address monitored by the testbench.

For example, the testbench might implement the [unofficial HTIF semihosting specification] and print the character A by writing the doubleword 0x01010000_00000041 to a label called tohost in the .data section of the test program. The most significant byte is the device (console), the next byte is the command (write), and the least significant 4 bytes are the data (the ASCII code for A). Terminating with a failure code is done by writing the doubleword 0x00000000_00000003 to tohost, and terminating with a success code is done by writing the doubleword 0x00000000_00000001 to tohost.

Note that writing the upper word of the doubleword to tohost with sd is only properly defined for RV64. Therefore, RV32 can use HTIF to terminate with a success or failure code but not necessarily to write to the console.

6.5. RVMODEL Macros for Other DUTs

If you have a simple DUT designed to match the behavior of Sail and Spike, you may be able to implement the RVMODEL macros with the same code used by Sail. Your RVMODEL_BOOT macro can be empty. The interrupt macros for unsupported privilege modes can be empty.

If you have a complex DUT, you presumably have a team of sophisticated verification engineers who can adapt the example macros to your DUT’s requirements.

6.6. Linker Script

Each DUT needs a linker script tailored to its memory map. The linker script in config/<core>/<version>/link.ld defines where to place the code and data regions in the DUT’s memory map. It must contain .text, .data, and .bss sections, and an ENTRY point named rvtest_entry_point. Users with special needs can customize the linker script to start at their own boot code (leaving the RVMODEL_BOOT macro blank) and then jump to rvtest_entry_point.

7. Architectural Functional Coverage

In principle, a test plan could simply list a set of features to test, and a set of tests that exercise these features. Experienced verification engineers have learned that tests often have bugs and don’t exercise the feature that the author intended. Many of these bugs can be caught if a different engineer independently writes functional coverpoints that measure whether the tests exercised the features.

This Certification Test Plan focuses on whether a DUT implements all of the architectural features of a profile. Architectural features are those that are directly visible to the programmer, especially those defined in the unprivileged and privileged ISA specifications.

Later phases of certification tests may add ratified architectural features outside the ISA spec, such as IOMMU, debug, or AIA.

Certification differs from design verification in that it does not systematically test microarchitectural features. Design verification must be aware of DUT-specific features such as the pipeline design. For example, DV should test design-specific interactions of interrupt arrival time, pipeline hazards, multicycle instructions, MMU, and memory system. Design verification also should test tricky implementation issues, such as hard floating-point rounding cases.

This plan uses the term Architectural Functional Coverage to describe the functional coverpoints required for certification. In contrast, full design verification also has Microarchitectural Functional Coverage.

Functional coverage also differs from code coverage, which measures whether the test suite exercises all of the lines of code in the RTL. Each of these detects different types of bugs. Code coverage is part of DV but not certification.

Architectural functional coverage requires a way to measure the architectural state of the machine after each instruction. The RISC-V Verification Interface (RVVI) provides a standard way to observe this state in the DUT. This document defines Extended RVVI with additional signals to facilitate testing virtual memory.

7.1. Extended RVVI

As compared to the base RVVI, Extended RVVI adds the following signals:

Table 6. Extended RVVI Signals
Signal Width Description

virt_adr_i

XLEN

Virtual address of instruction

virt_adr_d

XLEN

Virtual address of data accessed by instruction

phys_adr_i

PA_BITS

Physical address of instruction

phys_adr_d

PA_BITS

Physical address of data accessed by instruction

g_phys_adr_i

PA_BITS

Guest physical address of instruction (when Hypervisor is active, 0 when inactive)

g_phys_adr_d

PA_BITS

Guest physical address of data accessed by instruction (when Hypervisor is active, 0 when inactive)

pte_i

XLEN

Instruction page table entry (VS-stage when Hypervisor is active)

pte_d

XLEN

Data page table entry (VS-stage when Hypervisor is active)

g_pte_i

XLEN

Instruction page table entry (G-stage when Hypervisor is active, 0 when inactive)

g_pte_d

XLEN

Data page table entry (G-stage when Hypervisor is active, 0 when inactive)

page_type_i

3

Instruction page type (VS-stage when hypervisor is active))

page_type_d

3

Data page type (VS-stage when hypervisor is active))

g_page_type_i

3

Instruction page type (G-stage when hypervisor is inactive, 0 when inactive)

g_page_type_d

3

Data page type (G-stage when hypervisor is inactive, 0 when inactive)

tdata1[NTRIGGERS]

XLEN*NTRIGGERS

Sdtrig Trigger Data 1 for each debug trigger

tdata2[NTRIGGERS]

XLEN*NTRIGGERS

Sdtrig Trigger Data 2 for each debug trigger

tdata3[NTRIGGERS]

XLEN*NTRIGGERS

Sdtrig Trigger Data 3 for each debug trigger

tinfo[NTRIGGERS]

XLEN*NTRIGGERS

Sdtrig Trigger Info for each debug trigger
Table 7. Page Types
Code Type

000

kilopage

001

megapage

010

gigapage

011

terapage

100

petapage

other

reserved

Some accesses touch more than one physical page. Examples include misaligned accesses wrapping a page boundary, and some vector accesses. Extended RVVI provides the signals corresponding to the base address of the access. For vector, they correspond to the base address of the initial element access.

NTRIGGERS is a new parameter similar to FLEN defining the number of Sdtrig debug triggers supported by the platform.

7.2. riscvISACOV Signals

Coverpoints are described using the open riscvISACOV framework.

The framework collects data coming across the RVVI interface and presents it with ins.current and ins.prev data structures to allow easy access to the architectural state at the end of the current and previous instructions. For example, ins.current.rs1 is the source register for the current instruction, and ins.current.rd_val is the value written to the destination register by the current instruction.

Most coverpoints use ins.current, to measure architectural state at the end of the instruction. However, some privileged coverpoints need to know the privilege mode or values of CSRs at the start of the instruction and thus use ins.prev.

The available fields are given in framework/src/act/fcov/coverage/RISCV_coverage_rvvi.svh. Most commonly used fields are summarized in Table 8. Other fields include floating-point and vector register IDs and values, MMU extended RVVI signals, vector type information, and pending interrupts. TODO: handling register pairs.

Table 8. riscvISACOV Signals for Coverpoints
Signal Width Description Example

insn

ILEN

Instruction bit pattern

* add x10, x11, x12

inst_name

string

Instruction name

add

disass

string

Disassembled instruction

add x10, x11, x12

trap

1

Instruction trapped rather than retiring

0

mode

2

Privilege mode 11 = machine, 01 = supervisor, 00 = user

11

pc_rdata

XLEN

PC of current instruction

0x80000000

pc_wdata

XLEN

PC of next instruction

0x80000004

rs1

5

Source register 1 ID

11

rs2

5

Source register 2 ID

12

rd

5

Destination register ID

10

rs1_val

XLEN

Source register 1 value

42

rs2_val

XLEN

Source register 2 value

69

rd_val

XLEN

Value written to destination register

111

imm

XLEN

Value of immediate

100

csr

XLEN x 4096

Value of CSRs

  • exact meaning of trap, importance in writing test

RVVI and riscvISACOV support the notion of multiple harts that retire multiple instructions per cycle. The number of instructions retired per cycle is a microarchitectural issue irrelevant to architectural functional verification, so it is set to 1, consistent with simulators that report each instruction retiring individually. Phase 0-2 testing only involves a single hart. Later phases may need to generalize to multiple harts to exercise fences and atomic operations that relate to memory consistency.

Our riscvISACOV implementation uses a SystemVerilog disassembler in fcov/disassemble.svh, replacing a proprietary disassembler from Imperas. When adding new extensions, update the disassembler accordingly.

7.3. Writing Coverpoints with riscvISACOV

Move this and the remainder to ACT repo

  • example of coverpoint

  • organization of files

7.4. Sail Trace Coverage Flow

Coverage is measured by running tests on Sail and generating a RVVI-Trace file, then passing this file to an RVVI agent in a SystemVerilog testbench that checks coverage.

The number of coverpoints and the number of tests both grow with the number of extensions, so the runtime to measure coverage can grow quadratically with the number of extensions, and becomes problematic. To avoid this, it is recommended to only enable coverpoints for one extension (or small group of extensions) at a time and to only run tests for that extension, and generate a Unified Coverage Database (UDCB) file and report for that extension. A script will kick off such tests in parallel for all extensions, and merge the coverage reports.

Sail produces the trace file in a standard RVVI-Trace format (see Section Section 7.5). Any other simulator that implements the same trace format can also be used to cross-check coverage.

  • Jordan add instructions on how to run this

7.5. RVVI-Trace Format

  • Jordan write

  • how to handle instructions that change multiple CSRs, such as a write to mstatus.SIE also affecting sstatus.SIE

8. Reference Model

Certification may rely on a reference model (simulator) to compute the expected results of a test, such as sum of two numbers in an add instruction or the answer for a fsqrt.d instruction. Self-checking tests compare the result from the DUT against the expected result that was precomputed by the reference model and flag mismatches. Alternatively, the test may be generated with a set of one or more expected results for each test case (without a reference model), and the test can check that the DUT produces one of the expected results.

TODO: Discuss one vs. many reference models. RISC-V International has blessed Sail as the golden RISC-V model, so Sail is used as the reference model.

8.1. Deterministic, Nondeterministic, and Unspecified Behaviors

RISC-V feature behavior can be classified as deterministic, nondeterministic, and unspecified. Deterministic features have a unique expected value for a given configuration, such as the result of sub 1 - 2 on RV32. Nondeterministic features have a fine set of possible outcomes, and might vary unpredictably even on the same DUT. For example, vector tail-agnostic elements can preserve the input value or propagate all 1s, with no guarantee whether the same instruction has the same behavior on all elements or when executed twice in a row. Unspecified features, such as unimplemented instructions, could do anything, from being ignored, to predictably or unpredictably changing architectural state, to halting and catching fire.

All RISC-V simulators, when properly configured to match the behavior of a DUT, should produce the same answers as the DUT and each other for deterministic features. For nondeterministic features, they should produce one of the legal outcomes. For unspecified features, they can do anything.

Self-checking certification tests must check that the result of deterministic features match the reference model. Nondeterministic features must produce one of the finite set of legal outcomes, which must be provided by the test developer because a reference model only produces a single outcome. Unspecified features are not tested because there are no wrong answers.

This is harder than it seems because RISC-V has many features whose behaviors are not fully specified. Many of these features are not yet named, and the set of legal behaviors is not yet enumerated. Unified Database (UDB) is in the process of naming and enumerating all of these features and behaviors to fully describe the behavior of a DUT. Moreover, no simulator yet is fully configurable to match every feature. Some simulators, such as Spike, intentionally have a minimal set of configuration options and are hardwired to particular behaviors.

Nevertheless, Sail is making rapid progress and is aiming to fully implement the ratified RVA23 profile, read a UDB configuration, and support at least the most reasonable behaviors in time for certification.

8.2. List of Fundamentally Nondeterministic Behaviors

  • Mask- and tail-agnostic vector operations

    • Self-checking tests must accept undisturbed and all 1s in each element

  • Traps on misaligned accesses

    • If mtval is written with a nonzero value, it can be any address within the access***

    • When it also causes access fault / misaligned store, Allen has list of 7ish possible outcomes.

If nondeterministic behaviors are tested, the test must accept all legal outcomes. This is costly, so some nondeterministic behaviors may be untested. Nevertheless, agnostic vector operations will definitely be tested and accept all legal results.

When possible, the behavior should be made deterministic by a parameter such that the reference model can match the DUT with that parameter setting.

8.3. List of Theoretically Nondeterministic Behaviors with Configurable Deterministic Implementations

  • CSR WARL Fields: any legal value could be read, and the value is theoretically nondeterministic and could change from one write to another. UDB will define configurations with a single sensible behavior (such as all 0s), and we may limit certification to DUTs that implement a reasonable configuration.

Appendix A: Unprivileged Test Plan

Unprivileged tests exercise every instruction using every applicable source and destination register, and reasonable architectural edge values of sources. They are intended for certification, not verification. For example, they do not stress pipeline hazards.

The unprivileged test plan is written to be easily reviewed by a human, and to be automatically converted to machine-readable coverpoints and tests. It is defined with spreadsheets in comma-separated value (CSV) format.

A.1. Unprivileged Tests

Every bin in every coverpoint is associated with a specific test [3]. Unprivileged tests sweep some feature under test (such as the destination register rd) while randomizing all applicable register IDs and source values (including values to be loaded from memory). For example, the unprivileged test for the cp_rd coverpoint of the add instruction contains 32 add instructions, using the 32 different choices of rd. The rs1 and rs2 register numbers and values are selected randomly. [Appendix A: Examples] gives examples of unprivileged coverpoints and tests meeting these requirements and the coverpoints of Table 13 for the add instruction. Each test is self-checking, checking the destination register value against one provided by a reference model. Certain tests also test other state such as stores or floating-point flags, as described in those sections.

The random values are preferably selected in a deterministic way so that regenerating tests use the same random values where possible, minimizing differences between tests. This can be done by seeding the random number generator with a has of the instruction and coverpoint name.

Unprivileged tests are designed to never trap. Their results are independent of the privilege mode in which they are run, so they generally are run only in machine mode. They generally involve no privileged instructions, except that floating-point and vector tests turn on the mstatus.{FS/VS} bits to enable these extensions.

A.2. Unprivileged Coverpoints

The coverpoints in Table 9 are used in most of the unprivileged test plans in subsequent sections.

Table 9. Coverpoint Definitions
Coverpoint Bins Definition

Basic Coverpoints

cp_asm_count

1

Number of times the instruction is executed in the test, must be greater than 0.

cp_rs1

32

The rs1 register number used in the instruction.

cp_rs2

32

The rs2 register number used in the instruction.

cp_rd

32

The rd register number used in the instruction.

cp_rs1_edges

16

Edge values for rs1 (see Table 10).

cp_rs2_edges

16

Edge values for rs2 (see Table 10).

cp_imm_edges

20

Edge values for 12-bit immediates (see Table 11).

cr_rs1_imm_edges

16*20

Cross-product of rs1 and 12-bit immediate edges (see Table 11).

cr_rs1_rs2_edges

16*16

Cross-product of rs1 and rs2 edges, used for instructions with two source registers.

cmp_rs1_rs2

32

The rs1 and rs2 registers have the same register number.

cmp_rd_rs1

32

The rd register has the same register number as the rs1 register.

cmp_rd_rs2

32

The rd register has the same register number as the rs2 register.

cmp_rd_rs1_rs2

32

The rd register has the same register number as both the rs1 and rs2 registers.

cp_offset

2

A branch or jalr instruction has a positive and negative offset.

cp_uimm

XLEN

Exercise all XLEN unsigned immediate values, such as shift amounts.

cp_align

≤ 8

Alignment of naturally-aligned sub-doubleword load/store operand within doubleword

Coverpoints for Compressed Instructions

cp_rs1p

8

The rs1 register number used in compressed instructions supporting x8-x15.

cp_rs2p

8

The rs2 register number used in compressed instructions supporting x8-x15.

cp_rdp

8

The rd register number used in compressed instructions supporting x8-x15.

cp_fdp

8

The fd register number used in compressed floating-point instructions supporting x8-x15.

cp_fs2p

8

The fs2 register number used in compressed floating-point instructions supporting x8-x15.

cp_imm_mul

8

7-bit immediate that is a multiple of 4 (for word-sized load/store instructions).

Coverpoints for Floating-Point Instructions

cp_fs1

32

The fs1 register number used in the instruction.

cp_fs2

32

The fs2 register number used in the instruction.

cp_fs3

32

The fs3 register number used in the instruction.

cp_fd

32

The fd register number used in the instruction.

cp_fs1_edges

26

Edge values for fs1 (see Table 12)

cp_fs2_edges

26

Edge values for fs2 (see Table 12)

cp_fs3_edges

26

Edge values for fs3 (see Table 12)

cmp_fd_fs1

32

The fd register has the same register number as the fs1 register.

cmp_fd_fs2

32

The fd register has the same register number as the fs2 register.

cmp_fd_fs3

32

The fd register has the same register number as the fs3 register.

cp_frm

5

The floating-point rounding mode used in the instruction: rne, rdn, rup, rtz, rmm, dyn.

cp_csr_fflags

10

The instruction sets the {NV, DZ, OF, UF, NX} flags in the fflags CSR.

cp_csr_frm

6

Dynamic rounding mode in the frm CSR: rne, rdn, rup, rtz, rmm, illegal

cr_fs1_fs2_edges

26*26

Cross product of edges of fs1 and fs2 registers.

cr_fs1_fs3_edges

26*26

Cross product of edges of fs1 and fs3 registers.

cp_fclass

10

All 10 fclass classes.

cp_NaNBox

1

Upper bits of NaN-boxed value are all 1s

cp_fs1_badNB

12

The fs1 register contains an incorrectly-NaN-boxed lower-precision value.

cp_fs2_badNB

12

The fs2 register contains an incorrectly-NaN-boxed lower-precision value.

cp_fs3_badNB

12

The fs3 register contains an incorrectly-NaN-boxed lower-precision value.

cp_fpr_hazard

4

Floating-point register hazard detection: RAW, WAR, WAW, and no hazard.

Miscellaneous Coverpoints

cp_bs

4

Byte select field for 32-bit AES instructions

cp_rnum

11

Round number for AES instructions

Notes:

  • These coverpoints are adapted from the Imperas riscvISACOV functional coverage project.

  • Register number is a 5-bit ID (e.g. x7), while register value is an XLEN-sized number.

  • Most coverpoints typically have 32 bins because they exercise all 32 integer registers.

  • Cross-products exercise all combinations of two or more coverpoints. They can have a large number of bins.

  • Each of these coverpoints can optionally have a modifier appended. For example, cp_rs1_nx0 is a modified version of cp_rs1, covering all 31 rs1 register numbers excluding x0. It is used for load/store/jalr instructions that can’t rely on address 0 specified by x0 being legal. Modifiers are defined in the extensions that they apply to.

  • The cmp_* and cp_*_hazard coverpoints occupy the fuzzy land at the edge of certification and verification. They are included because they are easy.

  • The riscvISACOV test plan had cmp_rd_{rs1/rs2}_eqval coverpoints that compare if rd and one of the sources have the same value. These are generally hit by the cr_rs1_rs2_edges tests, so they don’t add interesting additional coverage and were dropped. riscvISACOV also had cp_{rs1/rs2/rd}_toggle tests that checked if each bit changed from 1 to 0 and vice versa. This is trivially exercised by providing all 0s followed by all 1s followed by al 0s again, so they were dropped.

Table 10. Integer Edge Case Definitions
Bin RV32 RV64

zero

00000000000000000000000000000000

0000000000000000000000000000000000000000000000000000000000000000

one

00000000000000000000000000000001

0000000000000000000000000000000000000000000000000000000000000001

two

00000000000000000000000000000010

0000000000000000000000000000000000000000000000000000000000000010

min

10000000000000000000000000000000

1000000000000000000000000000000000000000000000000000000000000000

minp1

10000000000000000000000000000001

1000000000000000000000000000000000000000000000000000000000000001

max

01111111111111111111111111111111

0111111111111111111111111111111111111111111111111111111111111111

maxm1

01111111111111111111111111111110

0111111111111111111111111111111111111111111111111111111111111110

ones

11111111111111111111111111111111

1111111111111111111111111111111111111111111111111111111111111111

onesm1

11111111111111111111111111111110

1111111111111111111111111111111111111111111111111111111111111110

walkeodd

10101010101010101010101010101010

1010101010101010101010101010101010101010101010101010101010101010

walkeven

01010101010101010101010101010101

0101010101010101010101010101010101010101010101010101010101010101

random

01???????????????????????????010

01???????????????????????????????????????????????????????????010

Wmax

n/a

0000000000000000000000000000000011111111111111111111111111111111

Wmaxm1

n/a

0000000000000000000000000000000011111111111111111111111111111110

Wmaxp1

n/a

0000000000000000000000000000000100000000000000000000000000000000

Wmaxp2

n/a

0000000000000000000000000000000100000000000000000000000000000001
Table 11. Immediate Edge Case Definitions (12-bit)
Bin 12-bit Signed Value

zero

0

p0

1

p1

2

three

3

p2

4

p3

8

p4

16

p5

32

p6

64

p7

128

p8

256

p9

512

hm1

1023

p10

1024

max

2047

min

-2048

minp1

-2047

onesm1

-2

ones

-1

randomp

1795
Table 12. Floating-Point Edge Case Definitions
Bin Half Float Double

pos0

0000

00000000

0000000000000000

neg0

8000

80000000

8000000000000000

pos1

3C00

3F800000

3FF0000000000000

neg1

BC00

BF800000

BFF0000000000000

pos1p5

3E00

3F000000

3FE0000000000000

neg1p5

BE00

BF000000

BFE0000000000000

pos2

4000

40000000

4000000000000000

neg2

C000

C0000000

C000000000000000

posminnorm

0400

00800000

0010000000000000

negminnorm

8400

80800000

8010000000000000

posmaxnorm

7BFF

7F7FFFFF

7FEFFFFFFFFFFFFF

negmaxnorm

FBFF

FF7FFFFF

FFEFFFFFFFFFFFFF

posmax_subnorm

03FF

007FFFFF

000FFFFFFFFFFFFF

negmax_subnorm

83FF

807FFFFF

800FFFFFFFFFFFFF

posmid_subnorm

0200

00400000

0008000000000000

negmid_subnorm

8200

80400000

8008000000000000

posmin_subnorm

0001

00000001

0000000000000001

negmin_subnorm

8001

80000001

8000000000000001

posinfinity

7C00

7F800000

7FF0000000000000

neginfinity

FC00

FF800000

FFF0000000000000

posQNaN

7E00-7FFF

7FC00000-7FFFFFFF

7FF8000000000000-7FFFFFFFFFFFFFFF

posSNaN

7C01-7DFF

7F800001-7FBFFFFF

7FF0000000000001-7FF7FFFFFFFFFFFF

negQNaN

FE00-FFFF

FFC00000-FFFFFFFF

FFF8000000000000-FFFFFFFFFFFFFFFF

negSNaN

FC01-FDFF

FF800001-FFBFFFFF

FFF0000000000001-FFF7FFFFFFFFFFFF

posrandom

58B4

7ef8654f

3FF58B4C00000000

negrandom

C93A

813d9ab0

A6E895993737426C

The register edge cases are selected to include extreme values and their immediate neighbors. They also include walking 1s and an arbitrary intermediate value. RV64 adds edge cases near the 32-bit boundary to stress W-type instructions. Immediate edge cases exercise each bit of the immediate, extreme values, and one random intermediate value.

A.3. I Base Integer Extension

Table 13 summarizes the coverpoints for the I extension. The Type column is used to generate tests with the appropriate operands. An x in the RV32 or RV64 column indicates that the instruction is supported in that XLEN. The remaining columns refer to coverpoints defined in Table 9.

Table 13. I Instruction Coverpoints
Instruction add addi addiw addw and andi auipc beq bge

Type

R

I

I

R

R

I

U

B

B

RV32

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_rs1

x

x

x

x

x

x

x

x

cp_rs2

x

x

x

x

x

cp_rd

x

x

x

x

x

x

x

cp_rs1_edges

x

x

x

x

x

x

x

x

cp_rs2_edges

x

x

x

x

x

cr_rs1_imm_edges

x

x

x

cr_rs1_rs2_edges

x

x

x

offset

offset

cmp_rs1_rs2

x

x

x

x

x

cmp_rd_rs1

x

x

x

x

x

x

cmp_rd_rs2

x

x

x

cmp_rd_rs1_rs2

x

x

x

cp_offset

x

x

cp_imm_edges

x

x

x

20bit

branch

branch
Instruction bgeu blt bltu bne fence jal jalr lb lbu

Type

B

B

B

B

F

J

JR

L

L

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_rs1

x

x

x

x

nx0

nx0

nx0

cp_rs2

x

x

x

x

cp_rd

x

x

x

x

cp_rs1_edges

x

x

x

x

cp_rs2_edges

x

x

x

x

cr_rs1_rs2_edges

offset

offset

offset

offset

cmp_rs1_rs2

x

x

x

x

cmp_rd_rs1

nx0

nx0

nx0

cp_offset

x

x

x

x

x

jalr

cp_imm_edges

branch

branch

branch

branch

jal

x

x

x

cp_align

byte

byte

cp_memval

byte

byte

cp_custom

fence
Instruction ld lh lhu lui lw lwu nop or ori

Type

L

L

L

U

L

L

I

R

I

RV32

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_rs1

nx0

nx0

nx0

nx0

nx0

x

x

cp_rs2

x

cp_rd

x

x

x

x

x

x

x

x

cp_rs1_edges

x

x

cp_rs2_edges

x

cr_rs1_imm_edges

x

cr_rs1_rs2_edges

x

cmp_rs1_rs2

x

cmp_rd_rs1

nx0

nx0

nx0

nx0

nx0

x

x

cmp_rd_rs2

x

cmp_rd_rs1_rs2

x

cp_imm_edges

x

x

x

20bit

x

x

x

cp_align

hword

hword

word

word

cp_memval

double

hword

hword

word

word
Instruction sb sd sh sll slli slliw sllw slt slti

Type

S

S

S

R

IS

ISW

R

R

I

RV32

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_rs1

nx0

nx0

nx0

x

x

x

x

x

x

cp_rs2

x

x

x

x

x

x

cp_rd

x

x

x

x

x

x

cp_rs1_edges

x

x

x

x

x

x

cp_rs2_edges

x

x

x

x

x

x

cr_rs1_imm_edges

uimm

uimmw

x

cr_rs1_rs2_edges

x

x

x

cmp_rs1_rs2

x

x

x

cmp_rd_rs1

x

x

x

x

x

x

cmp_rd_rs2

x

x

x

cmp_rd_rs1_rs2

x

x

x

cp_uimm

x

5

cp_imm_edges

x

x

x

x

cp_align

byte

hword
Instruction sltiu sltu sra srai sraiw sraw srl srli srliw

Type

I

R

R

IS

ISW

R

R

IS

ISW

RV32

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_rs1

x

x

x

x

x

x

x

x

x

cp_rs2

x

x

x

x

cp_rd

x

x

x

x

x

x

x

x

x

cp_rs1_edges

x

x

x

x

x

x

x

x

x

cp_rs2_edges

x

x

x

x

cr_rs1_imm_edges

x

uimm

uimmw

uimm

uimmw

cr_rs1_rs2_edges

x

x

x

x

cmp_rs1_rs2

x

x

x

x

cmp_rd_rs1

x

x

x

x

x

x

x

x

x

cmp_rd_rs2

x

x

x

x

cmp_rd_rs1_rs2

x

x

x

x

cp_uimm

x

5

x

5

cp_imm_edges

x
Instruction srlw sub subw sw xor xori

Type

R

R

R

S

R

I

RV32

x

x

x

x

RV64

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

cp_rs1

x

x

x

nx0

x

x

cp_rs2

x

x

x

x

x

cp_rd

x

x

x

x

x

cp_rs1_edges

x

x

x

x

x

cp_rs2_edges

x

x

x

x

x

cr_rs1_imm_edges

x

cr_rs1_rs2_edges

x

x

x

x

cmp_rs1_rs2

x

x

x

x

cmp_rd_rs1

x

x

x

x

x

cmp_rd_rs2

x

x

x

x

cmp_rd_rs1_rs2

x

x

x

x

cp_imm_edges

x

x

cp_align

word
Table 14. I Modified Coverpoints
Modified Coverpoint Bins Definition

cp_rs1_nx0

31

The rs1 register number used in the instruction, excluding x0. x0 is hardwired to 0, which results in potentially access faults for loads, stores, and jalr.

cmp_rd_rs1_nx0

31

See cp_rs1_nx0

cp_offset_jalr

6

cp_offset + 2*2 combinations of rs1_val[0] and imm[0] affecting lsb of jalr address

cp_uimm_5

32

5-bit unsigned immediate shift amount for {slliw/srliw/sraiw}

cp_imm_edges_20bit

27

20-bit variant of Table 11 for lui and auipc.

cp_imm_edges_jal

23

20-bit positive and negative jump offsets for jal. Note that testing the full 20-bit range takes a large amount of program memory, so tests may cover a subset of this range.

cp_align_{byte/hword/word}

8/4/2

Alignment of naturally-aligned load/store operand within doubleword in memory

cp_custom_fence

3

Test that fence, fence rw,rw, and fence.tso all execute without trapping.

Table 15 summarizes the normative rules in the RV{32/64}I specification and the unprivileged coverpoints that exercise them. Privileged coverpoints related to integer instructions are described in the relevant parts of Privileged Test Plan such as Sm and ExceptionsSm. In particular, ebreak and ecall are only tested in the Privileged test plan because their behavior is UNSPECIFIED without an mtvec trap vector CSR. Reserved behaviors are checked in Section B.6. Note that the testplans always test the following fundamental capabilities, even if no normative rule is cited:

  • Opcodes (cp_asm_count)

  • All Source and Destination Registers (cp_rs1, cp_rs2, cp_rd)

  • Edge values (cp_rs1_edges, cp_rs2_edges, cp_imm_edges, cr_rs1_rs2_edges, cr_rs1_imm_edges)

  • All other bitfields in the instruction

Table 15. I Normative Rules
Normative Rule Rule Text Coverpoints

rv32i_xreg_sz

For RV32I, the 32 x registers are each 32 bits wide, i.e., XLEN=32.

I_add_cg/{cp_rs1, cp_rs2, cp_rd, cr_rs1_rs2_edges}

rv32i_other_xregs

General purpose registers x1-x31 hold values that various instructions interpret as a collection of Boolean values, or as two’s complement signed binary integers or unsigned binary integers.

I_add_cg/{cp_rs1, cp_rs2, cp_rd, cr_rs1_rs2_edges}

pcreg_op

There is one additional unprivileged register: the program counter pc holds the address of the current instruction.

I_auipc_cg/cr_rs1_imm_edges

slti_op

SLTI (set less than immediate) places the value 1 in register rd if register rs1 is less than the sign-extended immediate when both are treated as signed numbers, else 0 is written to rd. SLTIU is similar but compares the values as unsigned numbers (i.e., the immediate is first sign-extended to XLEN bits then treated as an unsigned number).

I_slti_cg/{cp_rs1, cp_rd, cr_rs1_imm_edges}

sltiu_op

SLTI (set less than immediate) places the value 1 in register rd if register rs1 is less than the sign-extended immediate when both are treated as signed numbers, else 0 is written to rd. SLTIU is similar but compares the values as unsigned numbers (i.e., the immediate is first sign-extended to XLEN bits then treated as an unsigned number).

I_sltiu_cg/{cp_rs1, cp_rd, cr_rs1_imm_edges}

x0eq0

Register x0 is hardwired with all bits equal to 0.

I_add_cg/{cp_rs1, cp_rs2, cp_rd, cr_rs1_rs2_edges}

imm_always_sex

Except for the 5-bit immediates used in CSR instructions ([csrinsts]), immediates are always sign-extended

I_addi_cg/cr_rs1_imm_edges, I_lw_cg/cp_imm_edges, I_sw_cg/cp_imm_edges, I_lui_cg/cp_imm_edges_20bit, I_beq_cg/cp_imm_edges_branch, I_jal_cg/cp_offset

nop_op

The NOP instruction does not change any architecturally visible state, except for advancing the pc and incrementing any applicable performance counters.

I_nop_cg/{cp_asm_count}

addi_op

ADDI adds the sign-extended 12-bit immediate to register rs1.

I_addi_cg/{cp_rs1, cp_rd, cr_rs1_imm_edges}

addi_overflow

Arithmetic overflow is ignored and the result is simply the low XLEN bits of the result.

I_addi_cg/cr_rs1_imm_edges

andi_op, ori_op, xori_op

ANDI, ORI, XORI are logical operations that perform bitwise AND, OR, and XOR on register rs1 and the sign-extended 12-bit immediate and place the result in rd.

andi_op: I_andi_cg/{cp_rs1, cp_rd, cr_rs1_imm_edges}; ori_op: I_ori_op/{cp_rs1, cp_rd, cr_rs1_imm_edges}; xori_op: I_xori_op/{cp_rs1, cp_rd, cr_rs1_imm_edges}

slli_op

SLLI is a logical left shift (zeros are shifted into the lower bits);

I_slli_cg/{cp_rs1, cp_rd, cr_rs1_imm_edges_uimm}

srli_op

SRLI is a logical right shift (zeros are shifted into the upper bits);

I_srli_cg/{cp_rs1, cp_rd, cr_rs1_imm_edges_uimm}

srai_op

SRAI is an arithmetic right shift (the original sign bit is copied into the vacated upper bits).

I_srai_cg/{cp_rs1, cp_rd, cr_rs1_imm_edges_uimm}

lui_op

LUI places the 32-bit U-immediate value into the destination register rd, filling in the lowest 12 bits with zeros.

I_lui_cg/{cp_rd, cp_imm_edges_20bit}

auipc_op

AUIPC forms a 32-bit offset from the U-immediate, filling in the lowest 12 bits with zeros, adds this offset to the address of the AUIPC instruction, then places the result in register rd.

I_auipc_cg/{cp_rd, cp_imm_edges_20bit}

R-type_operands

All operations read the rs1 and rs2 registers as source operands and write the result into register rd.

{I_add_cg, I_sub_cg, I_and_cg, I_or_cg, I_xor_cg, I_sll_cg, I_srl_cg, I_sra_cg, I_slt_sg, I_sltu_cg}/{cp_rs1, cp_rs2, cp_rd, cmp_rs1_rs2, cmp_rd_rs1, cmp_rd_rs2, cmp_rd_rs1_rs2}

add_op

ADD performs the addition of rs1 and rs2.

I_add_cg/{cp_rs1, cp_rs2, cp_rd, cr_rs1_rs2_edges}

sub_op

SUB performs the subtraction of rs2 from rs1.

I_sub_cg/{cp_rs1, cp_rs2, cp_rd, cr_rs1_rs2_edges}

add_overflow, sub_overflow

Overflows are ignored and the low XLEN bits of results are written to the destination rd.

add_overflow: I_add_cg/cr_rs1_rs2_edges; sub_overflow: I_sub_cg/cr_rs1_rs2_edges

slt_op

SLT and SLTU perform signed and unsigned compares respectively, writing 1 to rd if rs1 < rs2, 0 otherwise.

I_slt_cg/{cp_rs1, cp_rs2, cp_rd, cr_rs1_rs2_edges}

sltu_op

SLT and SLTU perform signed and unsigned compares respectively, writing 1 to rd if rs1 < rs2, 0 otherwise.

I_sltu_cg/{cp_rs1, cp_rs2, cp_rd, cr_rs1_rs2_edges}

and_op, or_op, xor_op

AND, OR, and XOR perform bitwise logical operations.

and_op: I_and_cg/{cp_rs1, cp_rs2, cp_rd, cr_rs1_rs2_edges}; or_op: I_or_cg/{cp_rs1, cp_rs2, cp_rd, cr_rs1_rs2_edges}; xor_op: I_xor_cg/{cp_rs1, cp_rs2, cp_rd, cr_rs1_rs2_edges}

sll_op, srl_op, sra_op

SLL, SRL, and SRA perform logical left, logical right, and arithmetic right shifts on the value in register rs1 by the shift amount held in the lower 5 bits of register rs2.

sll_op: I_sll_cg/{cp_rs1, cp_rs2, cp_rd, cr_rs1_rs2_edges}; srl_op: I_srl_cg/{cp_rs1, cp_rs2, cp_rd, cr_rs1_rs2_edges}; sra_op: I_sra_cg/{cp_rs1, cp_rs2, cp_rd, cr_rs1_rs2_edges}

no_cti_delay_slots

Control transfer instructions in RV32I do not have architecturally visible delay slots.

{I_beq_cg, I_bne_cg, I_blt_cg, I_bltu_cg, I_bge_cg, I_bgeu_cg}/{cr_rs1_rs2_edges_offset}

jal_target

The offset is sign-extended and added to the address of the jump instruction to form the jump target address.

I_jal_cg/cp_offset

jal_op

JAL stores the address of the instruction following the jump ('pc'+4) into register rd.

I_jal_cg/{cp_rd}

jalr_target

The target address is obtained by adding the sign-extended 12-bit I-immediate to the register rs1, then setting the least-significant bit of the result to zero.

I_jalr_cg/{cp_imm_edges, cp_offset_lsbs}

jalr_op

The address of the instruction following the jump (pc+4) is written to register rd.

I_jalr_cg/{cp_rd}

br_target

The 12-bit B-immediate encodes signed offsets in multiples of 2 bytes. The offset is sign-extended and added to the address of the branch instruction to give the target address.

{I_beq_cg, I_bne_cg, I_blt_cg, I_bltu_cg, I_bge_cg, I_bgeu_cg}/{cr_rs1_rs2_edges_offset}

beq_op, bne_op

BEQ and BNE take the branch if registers rs1 and rs2 are equal or unequal respectively.

beq_op: I_beq_cg/{cp_rs1, cp_rs2, cr_rs1_rs2_edges_offset}; bne_op: I_bne_cg/{cp_rs1, cp_rs2, cr_rs1_rs2_edges_offset}

blt_op, bltu_op

BLT and BLTU take the branch if rs1 is less than rs2, using signed and unsigned comparison respectively.

blt_op: I_blt_cg/{cp_rs1, cp_rs2, cr_rs1_rs2_edges_offset}; bltu_op: I_bltu_cg/{cp_rs1, cp_rs2, cr_rs1_rs2_edges_offset}

bge_op, bgeu_op

BGE and BGEU take the branch if rs1 is greater than or equal to rs2, using signed and unsigned comparison respectively.

bge_op: I_bge_cg/{cp_rs1, cp_rs2, cr_rs1_rs2_edges_offset}; bgeu_op: I_bgeu_cg/{cp_rs1, cp_rs2, cr_rs1_rs2_edges_offset}

ldst_ea

The effective address is obtained by adding register rs1 to the sign-extended 12-bit offset.

{I_lw_op, I_lh_op, I_lhu_op, I_lb_op, I_lbu_op, I_sw_op, I_sh_op, I_sb_op}/{cp_imm_edges}

ldst_no_exc_aligned

loads and stores whose effective addresses are naturally aligned shall not raise an address-misaligned exception.

I_lw_cg/cp_align_word, I_lh_cg/cp_align_half, I_lhu_cg/cp_align_half, I_lb_cg/cp_align_byte, I_lbu_cg/cp_align_byte, I_sw_cg/cp_align_word, I_sh_cg/cp_align_half, I_sb_cg/cp_align_byte

load_op

Loads copy a value from memory to register rd.

I_lw_cg/{cp_memval_word}

store_op

Stores copy the value in register rs2 to memory.

I_sw_cg/{cp_rs2_edges}

lw_op

The LW instruction loads a 32-bit value from memory into rd.

I_lw_cg/{cp_rs1_nx0, cp_rd, cp_imm_edges, cp_memval_word}

lh_op

LH loads a 16-bit value from memory, then sign-extends to 32-bits before storing in rd.

I_lh_cg/{cp_rs1_nx0, cp_rd, cp_imm_edges, cp_memval_hword}

lhu_op

LHU loads a 16-bit value from memory but then zero extends to 32-bits before storing in rd.

I_lhu_cg/{cp_rs1_nx0, cp_rd, cp_imm_edges, cp_memval_hword}

lb_op

LB and LBU are defined analogously for 8-bit values. LH loads a 16-bit value from memory, then sign-extends to 32-bits before storing in rd.

I_lb_cg/{cp_rs1_nx0, cp_rd, cp_imm_edges, cp_memval_byte}

lbu_op

LB and LBU are defined analogously for 8-bit values. LHU loads a 16-bit value from memory but then zero extends to 32-bits before storing in rd.

I_lbu_cg/{cp_rd, cp_imm_edges, cp_memval_byte}

sw_op

The SW, SH, and SB instructions store 32-bit, 16-bit, and 8-bit values from the low bits of register rs2 to memory.

I_sw_cg/{cp_rs1_nx0, cp_rs2, cp_rs2_edges, cp_imm_edges}

sh_op

The SW, SH, and SB instructions store 32-bit, 16-bit, and 8-bit values from the low bits of register rs2 to memory.

I_sh_cg/{cp_rs1_nx0, cp_rs2, cp_rs2_edges, cp_imm_edges}

sb_op

The SW, SH, and SB instructions store 32-bit, 16-bit, and 8-bit values from the low bits of register rs2 to memory.

I_sb_cg/{cp_rs1_nx0, cp_rs2, cp_rs2_edges, cp_imm_edges}

ldst_atomicity_for_aligned

naturally aligned loads and stores are guaranteed to execute atomically

I_lw_cg/cp_align_word, I_lh_cg/cp_align_half, I_lhu_cg/cp_align_half, I_lb_cg/cp_align_byte, I_lbu_cg/cp_align_byte, I_sw_cg/cp_align_word, I_sh_cg/cp_align_half, I_sb_cg/cp_align_byte

fence_op

A FENCE (with fm=0000) orders all memory operations in its predecessor set before all memory operations in its successor set.

I_fence_cg/{cp_custom_fence}

fence-tso_op

FENCE.TSO orders all load operations in its predecessor set before all memory operations in its successor set, and all store operations in its predecessor set before all store operations in its successor set. This leaves non-AMO store operations in the FENCE.TSO’s predecessor set unordered with non-AMO loads in its successor set.

I_fence_cg/{cp_custom_fence}

fence-tso_ordering_rw_rw_ok

Because FENCE RW,RW imposes a superset of the orderings that FENCE.TSO imposes, it is correct to ignore the fm field and implement FENCE.TSO as FENCE RW,RW.

I_fence_cg/{cp_custom_fence}

fence_unused_flds_rsv

The unused fields in the FENCE instructions—​rs1 and rd—​are reserved for finer-grain fences in future extensions. For forward compatibility, base implementations shall ignore these fields

I_fence_cg/{cp_custom_fence}

fence_cons_ok

We chose a relaxed memory model to allow high performance from simple machine implementations and from likely future coprocessor or accelerator extensions. We separate out I/O ordering from memory R/W ordering to avoid unnecessary serialization within a device-driver hart and also to support alternative non-memory paths to control added coprocessors or I/O devices. Simple implementations may additionally ignore the predecessor and successor fields and always execute a conservative FENCE on all operations.

I_fence_cg/{cp_custom_fence}

hints_op

HINTs do not change any architecturally visible state, except for advancing the pc and any applicable performance counters. Implementations are always allowed to ignore the encoded hints.

I_add_cg/cp_rd, I_lui_cg/cp_rd, I_auipc_cg/cp_rd, I_addi_cg/cp_rd, I_andi_cg/cp_rd, I_ori_op/cp_rd, I_xori_op/cp_rd, I_sub_cg/cp_rd, I_and_cg/cp_rd, I_or_cg/cp_rd, I_xor_cg/cp_rd, I_sll_cg/cp_rd, I_srl_cg/cp_rd, I_sra_cg/cp_rd, I_fence_cg/cp_custom_fence

UDB Parameters: None.

Note that standard hints are mostly covered by testing integer instructions with rd = x0. fence hints are covered by the cp_custom_fence coverpoint. Ratified hints such as Zihintpause and Zihintntl are covered in Section A.10. Semihosting hints are not standardized or tested. Custom hints are not explicitly tested but the corresponding instructions are executed with rd = x0.

Table 16. rv64 Normative Rules
Normative Rule Rule Text Coverpoints

addiw_op

ADDIW is an RV64I instruction that adds the sign-extended 12-bit immediate to register rs1 and produces the proper sign extension of a 32-bit result in rd.

I_addw_cg/{cp_rs1, cp_rd, cr_rs1_imm_edges}

addiw_overflow

Overflows are ignored and the result is the low 32 bits of the result sign-extended to 64 bits.

I_addw_cg/cr_rs1_imm_edges

addw_op, subw_op

ADDW and SUBW are RV64I-only instructions that are defined analogously to ADD and SUB but operate on 32-bit values and produce signed 32-bit results.

addw_op: I_addw_cg/{cp_rs1, cp_rs2, cp_rd, cr_rs1_rs2_edges}; subw_op: I_subw_cg/{cp_rs1, cp_rs2, cp_rd, cr_rs1_rs2_edges}

addw_overflow

Overflows are ignored, and the low 32-bits of the result is sign-extended to 64-bits and written to the destination register.

I_addw_cg/cr_rs1_rs2_edges

auipc_op_rv64i

AUIPC forms a 32-bit offset from the U-immediate, filling in the lowest 12 bits with zeros, sign-extends the result to 64 bits, adds it to the address of the AUIPC instruction, then places the result in register rd.

I_auipc_cg/{cp_rd, cp_imm_edges_20bit}

lb_rv64i_op

The LD instruction loads a 64-bit value from memory into register rd for RV64I. The LW instruction loads a 32-bit value from memory and sign-extends this to 64 bits before storing it in register rd for RV64I. LH and LHU are defined analogously for 16-bit values, as are LB and LBU for 8-bit values.

I_lb_cg/cp_memval_byte

lbu_rv64i_op

The LD instruction loads a 64-bit value from memory into register rd for RV64I. The LW instruction loads a 32-bit value from memory and sign-extends this to 64 bits before storing it in register rd for RV64I. LH and LHU are defined analogously for 16-bit values, as are LB and LBU for 8-bit values.

I_lbu_cg/cp_memval_byte

ld_op_rv64i

The LD instruction loads a 64-bit value from memory into register rd for RV64I.

I_ld_cg/cp_memval_double

lh_op_rv64i

The LD instruction loads a 64-bit value from memory into register rd for RV64I. The LW instruction loads a 32-bit value from memory and sign-extends this to 64 bits before storing it in register rd for RV64I. LH and LHU are defined analogously for 16-bit values, as are LB and LBU for 8-bit values.

I_lh_cg/cp_memval_half

lhu_rv64i_op

The LD instruction loads a 64-bit value from memory into register rd for RV64I. The LW instruction loads a 32-bit value from memory and sign-extends this to 64 bits before storing it in register rd for RV64I. LH and LHU are defined analogously for 16-bit values, as are LB and LBU for 8-bit values.

I_lhu_cg/cp_memval_half

lui_op_rv64i

LUI places the 32-bit U-immediate into register rd, filling in the lowest 12 bits with zeros. The 32-bit result is sign-extended to 64 bits.

I_lui_cg/cp_imm_edges_20bit

lw_op_rv64i

The LW instruction loads a 32-bit value from memory and sign-extends this to 64 bits before storing it in register rd for RV64I.

I_lw_cg/cp_memval_word

lwu_op

The LWU instruction, on the other hand, zero-extends the 32-bit value from memory for RV64I.

I_lwu_cg/cp_memval_word

rv64_w_sex

These \"*W\" instructions ignore the upper 32 bits of their inputs and always produce 32-bit signed values, sign-extending them to 64 bits, i.e. bits XLEN-1 through 31 are equal.

{I_addw_cg, I_subw_cg, I_sllw_cg, I_srlw_cg, I_sraw_cg}/cr_rs1_rs2_edges

rv64i_other_xregs

General purpose registers x1-x31 hold values that various instructions interpret as a collection of Boolean values, or as two’s complement signed binary integers or unsigned binary integers.

I_addw_cg/{cp_rs1, cp_rs2, cp_rd, cr_rs1_rs2_edges}

rv64i_xreg_sz

RV64I widens the integer registers and supported user address space to 64 bits (XLEN=64 in [gprs]).

I_addw_cg/{cp_rs1, cp_rs2, cp_rd, cr_rs1_rs2_edges}

sb_op_rv64i

The SD, SW, SH, and SB instructions store 64-bit, 32-bit, 16-bit, and 8-bit values from the low bits of register rs2 to memory respectively.

I_sb_cg/cp_rs2_edges

sd_op_rv64i

The SD, SW, SH, and SB instructions store 64-bit, 32-bit, 16-bit, and 8-bit values from the low bits of register rs2 to memory respectively.

I_sd_cg/cp_rs2_edges

sh_op_rv64i

The SD, SW, SH, and SB instructions store 64-bit, 32-bit, 16-bit, and 8-bit values from the low bits of register rs2 to memory respectively.

I_sh_cg/cp_rs2_edges

sll_sh_amt_rv64i

In RV64I, only the low 6 bits of rs2 are considered for the shift amount.

I_sll_cg/cr_rs1_rs2_edges

slliw_imm5_rsv

SLLIW, SRLIW, and SRAIW encodings with imm[5] ≠ 0 are reserved.

I_slliw_cg/cp_uimm_5, See also Ssstrict in Section B.6

slliw_op

SLLIW, SRLIW, and SRAIW are RV64I-only instructions that are analogously defined but operate on 32-bit values and sign-extend their 32-bit results to 64 bits.

I_slliw_cg/{cp_rs1, cp_rd, cp_uimm_5, cr_rs1_imm_edges_uimm}

sllw_op

SLLW, SRLW, and SRAW are RV64I-only instructions that are analogously defined but operate on 32-bit values and sign-extend their 32-bit results to 64 bits. The shift amount is given by rs2[4:0].

I_sllw_cg/{cp_rs1, cp_rs2, cp_rd, cr_rs1_rs2_edges}

sra_sh_amt_rv64i

In RV64I, only the low 6 bits of rs2 are considered for the shift amount.

I_sra_cg/cr_rs1_rs2_edges

sraiw_imm5_rsv

SLLIW, SRLIW, and SRAIW encodings with imm[5] ≠ 0 are reserved.

I_sraiw_cg/cp_uimm_5, See also Ssstrict in Section B.6

sraiw_op

SLLIW, SRLIW, and SRAIW are RV64I-only instructions that are analogously defined but operate on 32-bit values and sign-extend their 32-bit results to 64 bits.

I_sraiw_cg/{cp_rs1, cp_rd, cp_uimm_5, cr_rs1_imm_edges_uimm}

sraw_op

SLLW, SRLW, and SRAW are RV64I-only instructions that are analogously defined but operate on 32-bit values and sign-extend their 32-bit results to 64 bits. The shift amount is given by rs2[4:0].

I_sraw_cg/{cp_rs1, cp_rs2, cp_rd, cr_rs1_rs2_edges}

srl_sh_amt_rv64i

In RV64I, only the low 6 bits of rs2 are considered for the shift amount.

I_srl_cg/cr_rs1_rs2_edges

srliw_imm5_rsv

SLLIW, SRLIW, and SRAIW encodings with imm[5] ≠ 0 are reserved.

I_srliw_cg/cp_uimm_5, See also Ssstrict in Section B.6

srliw_op

SLLIW, SRLIW, and SRAIW are RV64I-only instructions that are analogously defined but operate on 32-bit values and sign-extend their 32-bit results to 64 bits.

I_srliw_cg/{cp_rs1, cp_rd, cp_uimm_5, cr_rs1_imm_edges_uimm}

srlw_op

SLLW, SRLW, and SRAW are RV64I-only instructions that are analogously defined but operate on 32-bit values and sign-extend their 32-bit results to 64 bits. The shift amount is given by rs2[4:0].

I_srlw_cg/{cp_rs1, cp_rs2, cp_rd, cr_rs1_rs2_edges}

subw_overflow

Overflows are ignored, and the low 32-bits of the result is sign-extended to 64-bits and written to the destination register.

I_subw_cg/cr_rs1_imm_edges

sw_op_rv64i

The SD, SW, SH, and SB instructions store 64-bit, 32-bit, 16-bit, and 8-bit values from the low bits of register rs2 to memory respectively.

I_sw_cg/cp_rs2_edges

UDB Parameters: None.

A.4. M Multiply Extension

Table 17 summarizes the coverpoints for the M extension. Table 18 summarizes the relevant normative rules.

Table 17. M Instruction Coverpoints
Instruction div divu divuw divw mul mulh mulhsu mulhu mulw

Type

R

R

R

R

R

R

R

R

R

RV32

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_rs1

x

x

x

x

x

x

x

x

x

cp_rs2

x

x

x

x

x

x

x

x

x

cp_rd

x

x

x

x

x

x

x

x

x

cp_rs1_edges

x

x

x

x

x

x

x

x

x

cp_rs2_edges

x

x

x

x

x

x

x

x

x

cr_rs1_rs2_edges

x

x

x

x

x

x

x

x

x

cmp_rs1_rs2

x

x

x

x

x

x

x

x

x

cmp_rd_rs1

x

x

x

x

x

x

x

x

x

cmp_rd_rs2

x

x

x

x

x

x

x

x

x

cmp_rd_rs1_rs2

x

x

x

x

x

x

x

x

x
Instruction rem remu remuw remw

Type

R

R

R

R

RV32

x

x

RV64

x

x

x

x

cp_asm_count

x

x

x

x

cp_rs1

x

x

x

x

cp_rs2

x

x

x

x

cp_rd

x

x

x

x

cp_rs1_edges

x

x

x

x

cp_rs2_edges

x

x

x

x

cr_rs1_rs2_edges

x

x

x

x

cmp_rs1_rs2

x

x

x

x

cmp_rd_rs1

x

x

x

x

cmp_rd_rs2

x

x

x

x

cmp_rd_rs1_rs2

x

x

x

x
Table 18. M Normative Rules
Normative Rule Rule Text Coverpoints

mul_op

MUL performs an XLEN-bit×XLEN-bit multiplication of rs1 by rs2 and places the lower XLEN bits in the destination register.

M_mul_cg/{cp_rs1, cp_rs2, cp_rd, cr_rs1_rs2_edges}

mulh_op, mulhu_op, mulhsu_op

MULH, MULHU, and MULHSU perform the same multiplication but return the upper XLEN bits of the full 2×XLEN-bit product, for signed×signed, unsigned×unsigned, and rs1×unsigned rs2 multiplication.

mulh_op: M_mulh_cg/{cp_rs1, cp_rs2, cp_rd, cr_rs1_rs2_edges}; mulhu_op: M_mulhu_cg/{cp_rs1, cp_rs2, cp_rd, cr_rs1_rs2_edges}; mulhsu_op: M_mulhsu_cg/{cp_rs1, cp_rs2, cp_rd, cr_rs1_rs2_edges}

div_op, divu_op

DIV and DIVU perform an XLEN bits by XLEN bits signed and unsigned integer division of rs1 by rs2, rounding towards zero.

div_op: M_div_cg/{cp_rs1, cp_rs2, cp_rd, cr_rs1_rs2_edges}; divu_op: M_divu_op/{cp_rs1, cp_rs2, cp_rd, cr_rs1_rs2_edges}

divw_op, divuw_op

DIVW and DIVUW are RV64 instructions that divide the lower 32 bits of rs1 by the lower 32 bits of rs2, treating them as signed and unsigned integers, placing the 32-bit quotient in rd, sign-extended to 64 bits.

divw_op: M_divw_cg/{cp_rs1, cp_rs2, cp_rd, cr_rs1_rs2_edges}; divuw_op: M_divuw_op/{cp_rs1, cp_rs2, cp_rd, cr_rs1_rs2_edges}

rem_op, remu_op

REM and REMU provide the remainder of the corresponding division operation.

rem_op: M_rem_cg/{cp_rs1, cp_rs2, cp_rd, cr_rs1_rs2_edges}; remu_op: M_remu_op/{cp_rs1, cp_rs2, cp_rd, cr_rs1_rs2_edges}

remw_op, remuw_op

REMW and REMUW are RV64 instructions that provide the corresponding signed and unsigned remainder operations.

remw_op: M_remw_cg/{cp_rs1, cp_rs2, cp_rd, cr_rs1_rs2_edges}; remuw_op: M_remuw_op/{cp_rs1, cp_rs2, cp_rd, cr_rs1_rs2_edges}

div_by_zero

The quotient of division by zero has all bits set

{M_div_cg, M_divu_op}/{cr_rs1_rs2_edges}

rem_by_zero

the remainder of division by zero equals the dividend.

{M_rem_cg, M_remu_op}/{cr_rs1_rs2_edges}

signed_div_overflow

Signed division overflow occurs only when the most-negative integer is divided by −1. The quotient of a signed division with overflow is equal to the dividend, and the remainder is zero.

{M_rem_cg}/{cr_rs1_rs2_edges}

rem_result_sign

For REM, the sign of a nonzero result equals the sign of the dividend.

{M_rem_cg}/{cr_rs1_rs2_edges}

remw_result_sign, remuw_result_sign

Both REMW and REMUW always sign-extend the 32-bit result to 64 bits, including on a divide by zero.

{M_remw_cg/M_remuw_cg}/{cr_rs1_rs2_edges}

mulw_op

MULW is an RV64 instruction that multiplies the lower 32 bits of the source registers, placing the sign extension of the lower 32 bits of the result into the destination register.

M_mulw_cg/{cp_rs1, cp_rs2, cp_rd, cr_rs1_rs2_edges}

UDB Parameters: None.

A.4.1. Zmmul

The Zmmul extension is a subset of the M extension that includes only the multiply instructions. The coverpoints are listed in Table 19. If a configuration supports M, it implicitly also supports Zmmul, and thus these multiply instructions are tested twice. The runtime is negligible so multiplication is left in M to avoid confusion.

Table 19. Zmmul Instruction Coverpoints
Instruction mul mulh mulhsu mulhu mulw

Type

R

R

R

R

R

RV32

x

x

x

x

RV64

x

x

x

x

x

cp_asm_count

x

x

x

x

x

cp_rs1

x

x

x

x

x

cp_rs2

x

x

x

x

x

cp_rd

x

x

x

x

x

cp_rs1_edges

x

x

x

x

x

cp_rs2_edges

x

x

x

x

x

cr_rs1_rs2_edges

x

x

x

x

x

cmp_rs1_rs2

x

x

x

x

x

cmp_rd_rs1

x

x

x

x

x

cmp_rd_rs2

x

x

x

x

x

cmp_rd_rs1_rs2

x

x

x

x

x
Table 20. Zmmul Normative Rules
Normative Rule Rule Text Coverpoints

mul_op

MUL performs an XLEN-bit×XLEN-bit multiplication of rs1 by rs2 and places the lower XLEN bits in the destination register.

M_mul_cg/{cp_rs1, cp_rs2, cp_rd, cr_rs1_rs2_edges}

mulh_op, mulhu_op, mulhsu_op

MULH, MULHU, and MULHSU perform the same multiplication but return the upper XLEN bits of the full 2×XLEN-bit product, for signed×signed, unsigned×unsigned, and rs1×unsigned rs2 multiplication.

mulh_op: M_mulh_cg/{cp_rs1, cp_rs2, cp_rd, cr_rs1_rs2_edges}; mulhu_op: M_mulhu_cg/{cp_rs1, cp_rs2, cp_rd, cr_rs1_rs2_edges}; mulhsu_op: M_mulhsu_cg/{cp_rs1, cp_rs2, cp_rd, cr_rs1_rs2_edges}

mulw_op

MULW is an RV64 instruction that multiplies the lower 32 bits of the source registers, placing the sign extension of the lower 32 bits of the result into the destination register.

M_mulw_cg/{cp_rs1, cp_rs2, cp_rd, cr_rs1_rs2_edges}

UDB Parameters: None.

A.5. C Compressed Extension

The C extension is subdivided into Zca, Zcf, and Zcd. All configurations supporting C contain Zca. RV32CF configurations also contain Zcf, and RV{32/64}CD configurations also contain Zcd. A configuration supporting C should test all of the applicable Zc* extensions.

[t-C-priv-normative-rules] summarizes normative rules relating to compressed instructions affecting privileged behavior. ***update

A.5.1. Zca Compressed Extension

Table 21 summarizes the coverpoints for the Zca extension. These include standard compressed hints in the cp_custom_chint_* family (also called cp_chint_*). Note that some of the hints are also compressed Zihintntl hints. Custom compressed hints are not certified because they are custom.

Table 21. Zca Instruction Coverpoints
Instruction c.add c.addi c.addi16sp c.addi4spn c.addiw c.addw c.and c.andi c.beqz

Type

CR

CI

CI

CIW

CI

CA

CA

CBP

CB

RV32

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_rs1

nx0

nx0

nx0

p

p

p

p

cp_rs2

nx0

p

p

cp_rd

p

cp_rs1_edges

x

x

x

x

x

x

x

cp_rs2_edges

x

x

x

cr_rs1_imm_edges

6bit_n0

6bit

6bit

cr_rs1_rs2_edges

x

x

x

cmp_rs1_rs2

nx0

c

c

cp_offset

x

cp_imm_mul

addi16sp

addi4spn
Instruction c.bnez c.j c.jal c.jalr c.jr c.ld c.ldsp c.li c.lui

Type

CB

CJ

CJAL

CJALR

CJR

CL

CILS

CI

CIU

RV32

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_rs1

p

nx0

nx0

p

nx0

nx2

cp_rd

p

nx0

cp_rs1_edges

x

cmp_rd_rs1

c

cp_offset

x

x

x

c_jr

c_jr

cp_imm_edges

c_jal

c_jal

6bit

6bit_n0

cp_imm_mul

8

8sp
Instruction c.lw c.lwsp c.mv c.nop c.or c.sd c.sdsp c.slli c.srai

Type

CL

CILS

CR

CN

CA

CS

CSS

CIS

CBS

RV32

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_rs1

p

p

p

nx0

p

cp_rs2

nx0

p

p

x

cp_rd

p

nx0

nx0

cp_rs1_edges

x

x

x

cp_rs2_edges

x

x

x

x

cr_rs1_imm_edges

c

c

cr_rs1_rs2_edges

x

cmp_rs1_rs2

nx0

c

cmp_rd_rs1

c

cp_uimm

n0

n0

cp_imm_mul

x

4sp

8

8sp
Instruction c.srli c.sub c.subw c.sw c.swsp c.xor c.hint

Type

CBS

CA

CA

CS

CSS

CA

CI

RV32

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

cp_rs1

p

p

p

p

p

cp_rs2

p

p

p

x

p

cp_rs1_edges

x

x

x

x

cp_rs2_edges

x

x

x

x

x

cr_rs1_imm_edges

c

cr_rs1_rs2_edges

x

x

x

cmp_rs1_rs2

c

c

c

cp_uimm

n0

cp_imm_mul

x

4sp

cp_custom

chint

Modified coverpoints for Zc* are summarized in Table 22. As defined in Table 9, the p versions of coverpoints work on registers x8-x15.

Table 22. Zc Modified Coverpoints
Modified Coverpoint Bins Definition

cr_rs1_imm_edges_6bit

16*13

rs1 edges x Signed 6-bit immediates 0, 1, 2, 3, 4, 8 16, 30, 31, -32, -31, -2, -1

cr_rs1_imm_edges_6bit_n0

16*12

rs1 edges x cp_rs1_imm_edges_6bit excluding 0

cr_rs1_imm_edges_c

16*11

rs1 edges x unsigned 5 or 6-bit uimm 1, 2, 3, 4, 8, 14, 15, 16, 17, 30, 31. XLEN=64 adds 32, 33, 48, 62, 63

cp_imm_edges_c_jal

21

Selected signed multiples of 2 from -2048 to 1024

cmp_rs1_rs2_c

8

Same register x8-x15 for both rs1 and rs2 (and hence rd)

cp_imm_mul

31

Multiples of 4 from 0 to 124

cp_imm_mul_4sp

63

Multiples of 4 from 0 to 252

cp_imm_mul_8

31

Multiples of 4 from 0 to 248

cp_imm_mul_8sp

63

Multiples of 8 from 0 to 504

cp_imm_mul_addi16sp

63

Multiples of 16 from -512 to 496

cp_imm_mul_addi4spn

255

Multiples of 4 from 4 to 1020

cp_offset_jr

2 + 4

cp_offset + rs1_val[1:0] affecting lsb of load/store address

cp_custom_chint

63+31+64+63+31+31

Compressed standard hints using c.nop, c.addi, c.li, c.lui, c.mv, c.add
Table 23. Zca Normative Rules
Normative Rule Rule Text Coverpoints

Zca_offsets_mul2

As with base RVI instructions, the offsets of all RVC control transfer instructions are in multiples of 2 bytes.

Zca_c_beqz_cg/cp_offset, Zca_c_bnez_cg/cp_offset, Zca_c_j_cg/cp_offset, Zca_c_jal_cg/cp_offset, Zca_c_jalr_cg/cp_offset_c_jr, Zca_c_jr_cg/cp_offset_c_jr

Zca_regs8

CIW, CL, CS, CA, and CB are limited to just 8 of them. [registers] lists these popular registers, which correspond to registers x8 to x15.

Zca_c_and_cg/{cp_rs1p, cp_rs2p}

c-add_op

C.ADD adds the values in registers rd and rs2 and writes the result to register rd. C.ADD expands into add rd, rd, rs2.

Zca_c_add_cg/{cp_rs1_nx0, cp_rs2_nx0, cr_rs1_rs2_edges}

c-add_val

C.ADD is only valid when rs2≠x0; the code points with rs2=x0 correspond to the C.JALR and C.EBREAK instructions.

Zca_c_add_cg/{cp_rs1_nx0, cp_rs2_nx0}

c-addi16sp_op

C.ADDI16SP (add immediate to stack pointer) shares the opcode with C.LUI, but has a destination field of x2. C.ADDI16SP adds the non-zero sign-extended 6-bit immediate to the value in the stack pointer (sp=x2), where the immediate is scaled to represent multiples of 16 in the range [-512, 496]. C.ADDI16SP is used to adjust the stack pointer in procedure prologues and epilogues. It expands into addi x2, x2, nzimm[9:4].

Zca_c_addi16sp_cg/{cp_imm_mul_addi16sp}

c-addi4spn_op

C.ADDI4SPN (add immediate to stack pointer, non-destructive) is a CIW-format instruction that adds a zero-extended non-zero immediate, scaled by 4, to the stack pointer, x2, and writes the result to rd′. This instruction is used to generate pointers to stack-allocated variables, and expands to addi rd′, x2, nzuimm[9:2].

Zca_c_addi4spn_cg/{cp_imm_mul_addi4spn}

c-addi_nop

The code points with rd=x0 encode the C.NOP instruction, of which the code points with imm≠0 are HINTs.

Zca_c_nop_cg/{cp_asm_count}

c-addi_op

C.ADDI adds the non-zero sign-extended 6-bit immediate to the value in register rd then writes the result to rd. C.ADDI expands into addi rd, rd, imm.

Zca_c_addi_cg/{cp_rs1_nx0, cr_rs1_imm_edges_6bit_n0}

c-addiw_op

C.ADDIW is an RV64C-only instruction that performs the same computation but produces a 32-bit result, then sign-extends result to 64 bits. C.ADDIW expands into addiw rd, rd, imm. The immediate can be zero for C.ADDIW, where this corresponds to sext.w rd.

Zca_c_addiw_cg/{cp_rs1_nx0, cr_rs1_imm_edges_6bit}

c-addw_op

C.ADDW is an RV64C-only instruction that adds the values in registers rd′ and rs2′, then sign-extends the lower 32 bits of the sum before writing the result to register rd′. C.ADDW expands into addw rd′, rd′, rs2′.

Zca_c_addw_cg/{cp_rs1p, cp_rs2p, cr_rs1_rs2_edges}

c-and_op

C.AND computes the bitwise AND of the values in registers rd′ and rs2′, then writes the result to register rd′. C.AND expands into and rd′, rd′, rs2′.

Zca_c_and_cg/{cp_rs1p, cp_rs2p, cr_rs1_rs2_edges}

c-andi_op

C.ANDI is a CB-format instruction that computes the bitwise AND of the value in register rd′ and the sign-extended 6-bit immediate, then writes the result to rd′. C.ANDI expands to andi rd′, rd′, imm.

Zca_c_andi_cg/{cp_rs1p, cr_rs1_imm_edges_6bit}

c-beqz_op

C.BEQZ performs conditional control transfers. The offset is sign-extended and added to the pc to form the branch target address. It can therefore target a {pm}256 B range. C.BEQZ takes the branch if the value in register rs1′ is zero. It expands to beq rs1′, x0, offset.

Zca_c_beqz_cg/{cp_rs1p, cp_rs1_edges, cp_offset}

c-bnez_op

C.BNEZ is defined analogously, but it takes the branch if rs1′ contains a nonzero value. It expands to bne rs1′, x0, offset.

Zca_c_bnez_cg/{cp_rs1p, cp_rs1_edges, cp_offset}

c-j_op

C.J performs an unconditional control transfer. The offset is sign-extended and added to the pc to form the jump target address. C.J can therefore target a {pm}2 KiB range. C.J expands to jal x0, offset.

Zca_c_j_cg/{cp_imm_edges_c_jal}

c-jal_op

C.JAL is an RV32C-only instruction that performs the same operation as C.J, but additionally writes the address of the instruction following the jump (pc+2) to the link register, x1. C.JAL expands to jal x1, offset.

Zca_c_jal_cg/{cp_imm_edges_c_jal}

c-jalr_op

C.JALR (jump and link register) performs the same operation as C.JR, but additionally writes the address of the instruction following the jump (pc+2) to the link register, x1. C.JALR expands to jalr x1, 0(rs1).

Zca_c_jalr_cg/{cp_rs1_nx0, cp_offset_c_jr}

c-jr_op

C.JR (jump register) performs an unconditional control transfer to the address in register rs1. C.JR expands to jalr x0, 0(rs1).

Zca_c_jr_cg/{cp_rs1_nx0, cp_offset_c_jr}

c-ld_op

C.LD is an RV64C-only instruction that loads a 64-bit value from memory into register rd′. It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register rs1′. It expands to ld rd′, offset(rs1′).

Zca_c_ld_cg/{cp_rs1p, cp_rdp, cp_imm_mul_8}

c-ldsp_op

C.LDSP is an RV64C-only instruction that loads a 64-bit value from memory into register rd. It computes its effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, x2. It expands to ld rd, offset(x2).

Zca_c_ldsp_cg/{cp_rd_nx0, cp_imm_mul_8sp}

c-li_op

C.LI loads the sign-extended 6-bit immediate, imm, into register rd. C.LI expands into addi rd, x0, imm.

Zca_c_li_cg/{cp_rs1_nx0, cr_rs1_imm_edges_6bit}

c-lui_op

C.LUI loads the non-zero 6-bit immediate field into bits 17–12 of the destination register, clears the bottom 12 bits, and sign-extends bit 17 into all higher bits of the destination. C.LUI expands into lui rd, imm.

Zca_c_lui_cg/{cp_rs1_nx2, cr_rs1_imm_edges_6bit_n0}

c-lw_op

C.LW loads a 32-bit value from memory into register rd′. It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register rs1′. It expands to lw rd′, offset(rs1′).

Zca_c_lw_cg/{cp_rs1p, cp_rdp, cp_imm_mul}

c-lwsp_op

C.LWSP loads a 32-bit value from memory into register rd. It computes an effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, x2. It expands to lw rd, offset(x2).

Zca_c_lwsp_cg/{cp_rd_nx0, cp_imm_mul_4sp}

c-mv_jr

C.MV is valid only when rs2≠x0; the code points with rs2=x0 correspond to the C.JR instruction.

Zca_c_jr_cg/{cp_rs1_nx0, cp_offset_c_jr}

c-mv_op

C.MV copies the value in register rs2 into register rd. C.MV expands into add rd, x0, rs2.

Zca_c_mv_cg/{cp_rd_nx0, cp_rs2_nx0}

c-nop_op

C.NOP is a CI-format instruction that does not change any user-visible state, except for advancing the pc and incrementing any applicable performance counters. C.NOP expands to nop.

Zca_c_nop_cg/{cp_asm_count}

c-or_op

C.OR computes the bitwise OR of the values in registers rd′ and rs2′, then writes the result to register rd′. C.OR expands into or rd′, rd′, rs2′.

Zca_c_or_cg/{cp_rs1p, cp_rs2p, cr_rs1_rs2_edges}

c-sd_op

C.SD is an RV64C-only instruction that stores a 64-bit value in register rs2′ to memory. It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register rs1′. It expands to sd rs2′, offset(rs1′).

Zca_c_sd_cg/{cp_rs1p, cp_rs2p, cp_rs2_edges, cp_imm_mul_8}

c-sdsp_op

C.SDSP is an RV64C-only instruction that stores a 64-bit value in register rs2 to memory. It computes an effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, x2. It expands to sd rs2, offset(x2).

Zca_c_sdsp_cg/{cp_rs2, cp_rs2_edges, cp_imm_mul_8sp}

c-slli_op

C.SLLI is a CI-format instruction that performs a logical left shift of the value in register rd then writes the result to rd. The shift amount is encoded in the shamt field. C.SLLI expands into slli rd, rd, shamt[5:0].

Zca_c_slli_cg/{cp_rs1_nx0, cr_rs1_imm_edges_c}

c-slli_shamt5

For RV32C, shamt[5] must be zero; the code points with shamt[5]=1 are designated for custom extensions.

Zca_c_slli_cg/{cp_slli_uimm_n0}

c-srai_op

C.SRAI is defined analogously to C.SRLI, but instead performs an arithmetic right shift. C.SRAI expands to srai rd′, rd′, shamt.

Zca_c_srai_cg/{cp_rs1_p, cr_rs1_imm_edges_c}

c-srli_op

C.SRLI is a CB-format instruction that performs a logical right shift of the value in register rd′ then writes the result to rd′. The shift amount is encoded in the shamt field. C.SRLI expands into srli rd′, rd′, shamt.

Zca_c_srli_cg/{cp_rs1_p, cr_rs1_imm_edges_c}

c-srli_shamt5

For RV32C, shamt[5] must be zero; the code points with shamt[5]=1 are designated for custom extensions.

Zca_c_srli_cg/{cp_slli_uimm_n0}

c-sub_op

C.SUB subtracts the value in register rs2′ from the value in register rd′, then writes the result to register rd′. C.SUB expands into sub rd′, rd′, rs2′.

Zca_c_sub_cg/{cp_rs1p, cp_rs2p, cr_rs1_rs2_edges}

c-subw_op

C.SUBW is an RV64C-only instruction that subtracts the value in register rs2′ from the value in register rd′, then sign-extends the lower 32 bits of the difference before writing the result to register rd′. C.SUBW expands into subw rd′, rd′, rs2′.

Zca_c_subw_cg/{cp_rs1p, cp_rs2p, cr_rs1_rs2_edges}

c-sw_op

C.SW stores a 32-bit value in register rs2′ to memory. It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register rs1′. It expands to sw rs2′, offset(rs1′).

Zca_c_sw_cg/{cp_rs1p, cp_rs2p, cp_rs2_edges, cp_imm_mul}

c-swsp_op

C.SWSP stores a 32-bit value in register rs2 to memory. It computes an effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, x2. It expands to sw rs2, offset(x2).

Zca_c_swsp_cg/{cp_rs2, cp_rs2_edges, cp_imm_mul}

c-xor_op

C.XOR computes the bitwise XOR of the values in registers rd′ and rs2′, then writes the result to register rd′. C.XOR expands into xor rd′, rd′, rs2′.

Zca_c_xor_cg/{cp_rs1p, cp_rs2p, cr_rs1_rs2_edges}

Zca_hints

A portion of the RVC encoding space is reserved for microarchitectural HINTs. Like the HINTs in the RV32I base ISA (see [rv32i-hints]), these instructions do not modify any architectural state, except for advancing the pc and any applicable performance counters. HINTs are executed as no-ops on implementations that ignore them.

Zca_c_hint_cg/{cp_chint_add}

c-add_hint

The code points with rs2≠x0 and rd=x0 are HINTs.

Zca_c_hint_cg/{cp_chint_add}

c-addi_hint

The code points with rd≠0 and imm=0 are HINTs.

Zca_c_hint_cg/{cp_chint_addi}

c-li_hint

The C.LI code points with rd=x0 are HINTs.

Zca_c_hint_cg/{cp_chint_li}

c-lui_hint

The code points with rd=x0 and imm≠0 are HINTs.

Zca_c_hint_cg/{cp_chint_lui}

c-mv_hint

The code points with rs2≠x0 and rd=x0 are HINTs.

Zca_c_hint_cg/{cp_chint_mv}

c-nop_hint

The C.NOP code points with imm≠0 encode HINTs.

Zca_c_hint_cg/{cp_chint_nop}

c-slli_hint

The C.SLLI code points with shamt=0 or with rd=x0 are HINTs.

N/A custom hints not certified

c-srli_hint

The C.SRLI code points with shamt=0 are HINTs.

N/A custom hints not certified

c-sra_hint

N/A custom hints not certified

UDB Parameters: None.

A.5.2. Zcf Compressed Floating-Point Extension

Table 24 summarizes the coverpoints for the Zcf extension.

Table 24. Zcf Instruction Coverpoints
Instruction c.flw c.flwsp c.fsw c.fswsp

Type

CFL

CFLS

CFS

CFSS

RV32

x

x

x

x

cp_asm_count

x

x

x

x

cp_rs1

p

p

cp_fd

p

x

cp_fs2

p

x

cp_imm_mul

x

4sp

x

4sp
Table 25. Zcf Normative Rules
Normative Rule Rule Text Coverpoints

Zc_fp_regs

Compressed register-based floating-point loads and stores also use the CL and CS formats respectively, with the eight registers mapping to f8 to f15.

Zcf_c_flw_cg/{cp_fdp}

c-flw_op

C.FLW is an RV32FC-only instruction that loads a single-precision floating-point value from memory into floating-point register rd′. It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register rs1′. It expands to flw rd′, offset(rs1′).

Zcf_c_flw_cg/{cp_rs1p, cp_fdp, cp_imm_mul4}

c-flwsp_op

C.FLWSP is an RV32FC-only instruction that loads a single-precision floating-point value from memory into floating-point register rd. It computes its effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, x2. It expands to flw rd, offset(x2).

Zcf_c_flwsp_cg/{cp_rs1p, cp_fdp, cp_imm_mul4sp}

c-fsw_op

C.FSW is an RV32FC-only instruction that stores a single-precision floating-point value in floating-point register rs2′ to memory. It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register rs1′. It expands to fsw rs2′, offset(rs1′).

Zcf_c_fsw_cg/{cp_rs1p, cp_fs2p, cp_imm_mul4}

c-fswsp_op

C.FSWSP is an RV32FC-only instruction that stores a single-precision floating-point value in floating-point register rs2 to memory. It computes an effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, x2. It expands to fsw rs2, offset(x2).

Zcf_c_fswsp_cg/{cp_rs1p, cp_fs2p, cp_imm_mul4sp}

UDB Parameters: None.

A.5.3. Zcd Compressed Double-Precision FP Extension

Table 26 summarizes the coverpoints for the Zcd extension.

Table 26. Zcd Instruction Coverpoints
Instruction c.fld c.fldsp c.fsd c.fsdsp

Type

CFL

CFLS

CFS

CFSS

RV32

x

x

x

x

RV64

x

x

x

x

cp_asm_count

x

x

x

x

cp_rs1

p

p

cp_fd

p

x

cp_fs2

p

x

cp_imm_mul

8

8sp

8

8sp
Table 27. Zcd Normative Rules
Normative Rule Rule Text Coverpoints

Zc_fp_regs

Compressed register-based floating-point loads and stores also use the CL and CS formats respectively, with the eight registers mapping to f8 to f15.

Zcd_c_fld_cg/{cp_fdp}

c-fldsp_op

C.FLDSP is an RV32DC/RV64DC-only instruction that loads a double-precision floating-point value from memory into floating-point register rd. It computes its effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, x2. It expands to fld rd, offset(x2).

Zcf_c_fldsp_cg/{cp_rs1p, cp_fdp, cp_imm_mul8sp}

c-fld_op

C.FLD is an RV32DC/RV64DC-only instruction that loads a double-precision floating-point value from memory into floating-point register rd′. It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register rs1′. It expands to fld rd′, offset(rs1′).

Zcf_c_fld_cg/{cp_rs1p, cp_fdp, cp_imm_mul8}

c-fsd_op

C.FSD is an RV32DC/RV64DC-only instruction that stores a double-precision floating-point value in floating-point register rs2′ to memory. It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register rs1′. It expands to fsd rs2′, offset(rs1′).

Zcf_c_fsd_cg/{cp_rs1p, cp_fs2p, cp_imm_mul8}

c-fsdwsp_op

C.FSDSP is an RV32DC/RV64DC-only instruction that stores a double-precision floating-point value in floating-point register rs2 to memory. It computes an effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, x2. It expands to fsd rs2, offset(x2).

Zcf_c_fsdwsp_cg/{cp_rs1p, cp_fs2p, cp_imm_mul8sp}

UDB Parameters: None.

A.5.4. Zcb Additional Compressed Instructions

Table 28 summarizes the coverpoints for the Zcb extension.

Table 28. Zcb Instruction Coverpoints
Instruction c.lbu c.lh c.lhu c.not c.sb c.sh c.zext.b

Type

CLB

CLH

CLH

CU

CSB

CSH

CU

RV32

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

cp_rs1

p

p

p

p

p

p

p

cp_rs2

p

p

cp_rd

p

p

p

cp_rs1_edges

x

x

cp_rs2_edges

x

x

cmp_rd_rs1

c

c

c
Table 29. Zcb Normative Rules
Normative Rule Rule Text Coverpoints

c-lbu_op

loads a byte from the memory address formed by adding rs1' to the zero extended immediate uimm. The resulting byte is zero extended to XLEN bits and is written to rd'.

Zcb_c_lbu_cg/{cp_rs1p, cp_rdp}

c-lh_op

loads a halfword from the memory address formed by adding rs1' to the zero extended immediate uimm. The resulting halfword is sign extended to XLEN bits and is written to rd'.

Zcb_c_lh_cg/{cp_rs1p, cp_rdp}

c-lhu_op

loads a halfword from the memory address formed by adding rs1' to the zero extended immediate uimm. The resulting halfword is zero extended to XLEN bits and is written to rd'.

Zcb_c_lhu_cg/{cp_rs1p, cp_rdp}

c-not_op

takes the one’s complement of rd'/rs1' and writes the result to the same register.

Zcb_c_not_cg/{cp_rs1p, cp_rs1_edges}

c-sb_op

stores the least significant byte of rs2' to the memory address formed by adding rs1' to the zero extended immediate uimm.

Zcb_c_sb_cg/{cp_rs1p, cp_rs2p}

c-sh_op

stores the least significant halfword of rs2' to the memory address formed by adding rs1' to the zero extended immediate uimm.

Zcb_c_sh_cg/{cp_rs1p, cp_rs2p}

c-zext-b_op

zero-extends the least-significant byte of the operand to XLEN bits by inserting zeros into all of the bits more significant than 7.

Zcb_c_zext_b_cg/{cp_rs1p, cp_rs1_edges}

UDB Parameters: None.

A.5.4.1. ZcbM

When both Zcb and M are supported, add the instruction in Table 30 to the Zcb coverpoints.

Table 30. ZcbM Instruction Coverpoints
Instruction c.mul

Type

CA

RV32

x

RV64

x

cp_asm_count

x

cp_rs1

p

cp_rs2

p

cp_rs1_edges

x

cp_rs2_edges

x

cr_rs1_rs2_edges

x

cmp_rs1_rs2

c
Table 31. ZcbM Normative Rules
Normative Rule Rule Text Coverpoints

c-mul_op

multiplies XLEN bits of the source operands from rsd' and rs2' and writes the lowest XLEN bits of the result to rsd'.

Zcb_c_mul_cg/{cp_rs1p, cp_rs2p, cr_rs1_rs2_edges}

UDB Parameters: None.

A.5.4.2. ZcbZba

When both Zcb and Zba are supported, add the instruction in Table 32 to the Zcb coverpoints.

Table 32. ZcbZba Instruction Coverpoints
Instruction c.zext.w

Type

CU

RV64

x

cp_asm_count

x

cp_rs1

p

cp_rs1_edges

x
Table 33. ZcbZba Normative Rules
Normative Rule Rule Text Coverpoints

c-zext-w_op

zero-extends the least-significant word of the operand to XLEN bits by inserting zeros into all of the bits more significant than 31.

Zcb_c_zext_w_cg/{cp_rs1p, cp_rs1_edges}

UDB Parameters: None.

A.5.4.3. ZcbZbb

When both Zcb and Zbb are supported, add the instructions in Table 34 to the Zcb coverpoints.

Table 34. ZcbZbb Instruction Coverpoints
Instruction c.sext.b c.sext.h c.zext.h

Type

CU

CU

CU

RV32

x

x

x

RV64

x

x

x

cp_asm_count

x

x

x

cp_rs1

p

p

p

cp_rs1_edges

x

x

x
Table 35. ZcbZbb Normative Rules
Normative Rule Rule Text Coverpoints

c-sext-b_op

sign-extends the least-significant byte in the operand to XLEN bits by copying the most-significant bit in the byte (i.e., bit 7) to all of the more-significant bits.

Zcb_c_sext_b_cg/{cp_rs1p, cp_rs1_edges}

c-sext-h_op

sign-extends the least-significant halfword in the operand to XLEN bits by copying the most-significant bit in the halfword (i.e., bit 15) to all of the more-significant bits.

Zcb_c_sext_h_cg/{cp_rs1p, cp_rs1_edges}

c-zext-h_op

zero-extends the least-significant halfword of the operand to XLEN bits by inserting zeros into all of the bits more significant than 15.

Zcb_c_zext_h_cg/{cp_rs1p, cp_rs1_edges}

UDB Parameters: None.

A.6. A Atomic Extension

The A extension is subdivided into Zaamo and Zalrsc.

This section exercises unprivileged tests that will not trap. Privileged tests are in other sections, such as ExceptionsZaamo.

A.6.1. Zaamo Atomic Memory Operations Extension

Table 36 summarizes the coverpoints for the Zaamo extension.

Table 36. Zaamo Instruction Coverpoints
Instruction amoadd.d amoadd.w amoand.d amoand.w amomax.d amomax.w amomaxu.d amomaxu.w amomin.d

Type

A

A

A

A

A

A

A

A

A

RV32

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_rs1

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

cp_rs2

x

x

x

x

x

x

x

x

x

cp_rd

x

x

x

x

x

x

x

x

x

cp_rs2_edges

x

x

x

x

x

x

x

x

x

cmp_rs1_rs2

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

cmp_rd_rs1

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

cmp_rd_rs2

x

x

x

x

x

x

x

x

x

cmp_rd_rs1_rs2

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

cp_align

word

word

word

word
Instruction amomin.w amominu.d amominu.w amoor.d amoor.w amoswap.d amoswap.w amoxor.d amoxor.w

Type

A

A

A

A

A

A

A

A

A

RV32

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_rs1

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

cp_rs2

x

x

x

x

x

x

x

x

x

cp_rd

x

x

x

x

x

x

x

x

x

cp_rs2_edges

x

x

x

x

x

x

x

x

x

cmp_rs1_rs2

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

cmp_rd_rs1

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

cmp_rd_rs2

x

x

x

x

x

x

x

x

x

cmp_rd_rs1_rs2

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

cp_align

word

word

word

word

word
Table 37. Zaamo Normative Rules
Normative Rule Rule Text Coverpoints

a_aq_rl_bits

each atomic instruction has two bits, aq and rl, used to specify additional memory ordering constraints as viewed by other RISC-V harts.

TODO add coverpoint cp_custom_aqrl like Zalrsc

amo_release_consistency

To help implement multiprocessor synchronization, the AMOs optionally provide release consistency semantics. If the aq bit is set, then no later memory operations in this RISC-V hart can be observed to take place before the AMO. Conversely, if the rl bit is set, then other RISC-V harts will not observe the AMO before memory accesses preceding the AMO in this RISC-V hart. Setting both the aq and the rl bit on an AMO makes the sequence sequentially consistent, meaning that it cannot be reordered with earlier or later memory operations from the same hart.

OUT-OF-SCOPE for single hart

a_domain_specific_ordering

The bits order accesses to one of the two address domains, memory or I/O, depending on which address domain the atomic instruction is accessing. No ordering constraint is implied to accesses to the other domain, and a FENCE instruction should be used to order across both domains.

OUT-OF-SCOPE for single hart

a_no_aq_rl

If both bits are clear, no additional ordering constraints are imposed on the atomic memory operation.

OUT-OF-SCOPE for single hart

a_acquire_semantics

If only the aq bit is set, the atomic memory operation is treated as an acquire access, i.e., no following memory operations on this RISC-V hart can be observed to take place before the acquire memory operation.

OUT-OF-SCOPE for single hart

a_release_semantics

If only the rl bit is set, the atomic memory operation is treated as a release access, i.e., the release memory operation cannot be observed to take place before any earlier memory operations on this RISC-V hart.

OUT-OF-SCOPE for single hart

a_seq_cst_semantics

If both the aq and rl bits are set, the atomic memory operation is sequentially consistent and cannot be observed to happen before any earlier memory operations or after any later memory operations in the same RISC-V hart and to the same address domain.

OUT-OF-SCOPE for single hart

amo_operand_size

AMOs can either operate on doublewords (RV64 only) or words in memory. For RV64, 32-bit AMOs always sign-extend the value placed in rd, and ignore the upper 32 bits of the original value of rs2.

{Zaamo_amoadd_w_cg, Zaamo_amoadd_d_cg}/cp_rs2_edges

amo_alignment

For AMOs, the Zaamo extension requires that the address held in rs1 be naturally aligned to the size of the operand (i.e., eight-byte aligned for doublewords and four-byte aligned for words).

Zaamo_amoadd_w_cg/cp_align_word

UDB Parameters: None.

This test suite is unprivileged and does not perform misaligned accesses. The MISALIGNED_AMO parameter affects the expected results of ExceptionsZaamo/cp_amo_address_misaligned (Table 152).

A.6.2. Zalrsc Load-Reserved / Store-Conditional Extension

Table 38 summarizes the coverpoints for the Zalrsc extension.

Table 38. Zalrsc Instruction Coverpoints
Instruction lr.d lr.w sc.d sc.w

Type

LR

LR

SC

SC

RV32

x

x

RV64

x

x

x

x

cp_asm_count

x

x

x

x

cp_rs1

nx0

nx0

nx0

nx0

cp_rs2

x

x

cp_rd

x

x

x

x

cp_rs2_edges

x

x

cmp_rs1_rs2

nx0

nx0

cmp_rd_rs1

nx0

nx0

nx0

nx0

cmp_rd_rs2

x

x

cmp_rd_rs1_rs2

nx0

nx0

cp_custom

lr

lr

sc

sc
Table 39. Zalrsc Coverpoint Definitions
Coverpoint Bins Definition

cp_custom_lr coverpoints

cp_custom_aqrl

3

none, aq, aqrl

cp_custom_rd_edges

3

rd_value = 0, 1, -1

cp_custom_sc coverpoints

cp_custom_aqrl

3

none, rl, aqrl

cp_custom_sc_after_sc

2

sc followed by sc

cp_custom_sc_after_store

4

store followed by sc

cp_custom_sc_after_load

6

load followed by sc

cp_custom_sc_lrsc

2

lr followed by sc that fails and passes

cp_custom_sc_addresses

32*2

lr followed by sc at address of 8, …​, 248 offset from lr address. For RV64, exercise both lr.d and lr.w
Table 40. Zalrsc Normative Rules
Normative Rule Rule Text Coverpoints

a_aq_rl_bits

each atomic instruction has two bits, aq and rl, used to specify additional memory ordering constraints as viewed by other RISC-V harts.

Zalrsc_lr_w_cg/cp_custom_aqrl

a_domain_specific_ordering

The bits order accesses to one of the two address domains, memory or I/O, depending on which address domain the atomic instruction is accessing. No ordering constraint is implied to accesses to the other domain, and a FENCE instruction should be used to order across both domains.

OUT-OF-SCOPE for single hart

a_no_aq_rl

If both bits are clear, no additional ordering constraints are imposed on the atomic memory operation.

OUT-OF-SCOPE for single hart

a_acquire_semantics

If only the aq bit is set, the atomic memory operation is treated as an acquire access, i.e., no following memory operations on this RISC-V hart can be observed to take place before the acquire memory operation.

OUT-OF-SCOPE for single hart

a_release_semantics

If only the rl bit is set, the atomic memory operation is treated as a release access, i.e., the release memory operation cannot be observed to take place before any earlier memory operations on this RISC-V hart.

OUT-OF-SCOPE for single hart

a_seq_cst_semantics

If both the aq and rl bits are set, the atomic memory operation is sequentially consistent and cannot be observed to happen before any earlier memory operations or after any later memory operations in the same RISC-V hart and to the same address domain.

OUT-OF-SCOPE for single hart

lr_w_op

LR.W loads a word from the address in rs1, places the sign-extended value in rd, and registers a reservation set—a set of bytes that subsumes the bytes in the addressed word.

Zalrsc_lr_w_cg/{cp_rs1_nx0, cp_rd}

sc_w_success

SC.W conditionally writes a word in rs2 to the address in rs1: the SC.W succeeds only if the reservation is still valid and the reservation set contains the bytes being written. If the SC.W succeeds, the instruction writes the word in rs2 to memory, and it writes zero to rd.

Zalrsc_sc_w_cg/cp_sc_fail

sc_w_failure

If the SC.W fails, the instruction does not write to memory, and it writes a nonzero value to rd.

Zalrsc_sc_w_cg/cp_sc_fail

sc_failed_side_effects

but it is UNSPECIFIED whether any side effects of implicit address translation and protection memory accesses (such as setting a page-table entry D bit) occur on a failed SC.W.

NONE: Behavior is UNSPECIFIED and OUT-OF-SCOPE

sc_reservation_invalidate

Regardless of success or failure, executing an SC.W instruction invalidates any reservation held by this hart.

Zalrsc_sc_w_cg/cp_custom_sc_after_sc

lr_sc_rv64

LR.D and SC.D act analogously on doublewords and are only available on RV64. For RV64, LR.W and SC.W sign-extend the value placed in rd.

Zalrsc_lr_d_cg/{cp_rs1_nx0, cp_rd}, Zalrsc_sc_d_cg/cp_sc_fail

sc_failure_code

The failure code with value 1 encodes an unspecified failure. Other failure codes are reserved at this time. Portable software should only assume the failure code will be non-zero.

Zalrsc_sc_w_cg/cp_sc_fail

lr_reservation_set_size

An implementation can register an arbitrarily large reservation set on each LR, provided the reservation set includes all bytes of the addressed data word or doubleword.

Zalrsc_sc_w_cg/cp_custom_sc_addresseses

sc_pairs_latest_lr

An SC can only pair with the most recent LR in program order.

TODO

sc_success_conditions

An SC may succeed only if no store from another hart to the reservation set can be observed to have occurred between the LR and the SC, and if there is no other SC between the LR and itself in program order.

Zalrsc_sc_w_cg/cp_custom_sc_after_sc; multihart not tested

sc_device_write_failure

An SC may succeed only if no write from a device other than a hart to the bytes accessed by the LR instruction can be observed to have occurred between the LR and SC.

OUT-OF-SCOPE: device writes not modeled

sc_addr_not_in_reservation_fail

The SC must fail if the address is not within the reservation set of the most recent LR in program order.

Zalrsc_sc_w_cg/cp_sc_fail

sc_other_hart_store_fail

The SC must fail if a store to the reservation set from another hart can be observed to occur between the LR and SC.

OUT-OF-SCOPE for single hart

sc_other_device_write_fail

The SC must fail if a write from some other device to the bytes accessed by the LR can be observed to occur between the LR and SC.

OUT-OF-SCOPE: device writes not modeled

sc_intervening_sc_fail

An SC must fail if there is another SC (to any address) between the LR and the SC in program order.

Zalrsc_sc_w_cg/cp_custom_sc_after_sc

lr_sc_atomicity_axiom

The precise statement of the atomicity requirements for successful LR/SC sequences is defined by the Atomicity Axiom in [rvwmo].

OUT-OF-SCOPE for single hart

sc_not_observable_before_lr

An SC instruction can never be observed by another RISC-V hart before the LR instruction that established the reservation.

OUT-OF-SCOPE for single hart

lr_sc_aq_rl_software_rule

Software should not set the rl bit on an LR instruction unless the aq bit is also set, nor should software set the aq bit on an SC instruction unless the rl bit is also set. LR.rl and SC.aq instructions are not guaranteed to provide any stronger ordering than those with both bits clear, but may result in lower performance.

Nothing to test

constrained_lrsc_loop_size

The loop comprises only an LR/SC sequence and code to retry the sequence in the case of failure, and must comprise at most 16 instructions placed sequentially in memory.

Untested

constrained_lrsc_instruction_set

An LR/SC sequence begins with an LR instruction and ends with an SC instruction. The dynamic code executed between the LR and SC instructions can only contain instructions from the base ''I'' instruction set, excluding loads, stores, backward jumps, taken backward branches, JALR, FENCE, and SYSTEM instructions.

Untested

constrained_lrsc_compressed_allowed

Compressed forms of the aforementioned ''I'' instructions in the C (hence Zca) and Zcb extensions are also permitted.

Untested

constrained_lrsc_retry_code

The code to retry a failing LR/SC sequence can contain backwards jumps and/or branches to repeat the LR/SC sequence, but otherwise has the same constraint as the code between the LR and SC.

Untested

lrsc_eventuality_region

The LR and SC addresses must lie within a memory region with the LR/SC eventuality property. The execution environment is responsible for communicating which regions have this property.

Untested

lrsc_same_address_and_size

The SC must be to the same effective address and of the same data size as the latest LR executed by the same hart.

Zalrsc_sc_w_cg/cp_custom_sc_addresses

unconstrained_lrsc_no_progress

LR/SC sequences that do not lie within constrained LR/SC loops are unconstrained. Unconstrained LR/SC sequences might succeed on some attempts on some implementations, but might never succeed on other implementations.

Untested
Table 41. Zalrsc UDB Parameters
Parameter Description Coverpoint Effect

LRSC_RESERVATION_STRATEGY

Strategy used to handle reservation sets.

* "reserve naturally-aligned 64-byte region": Always reserve the 64-byte block containing the LR/SC address * "reserve naturally-aligned 128-byte region": Always reserve the 128-byte block containing the LR/SC address * "reserve exactly enough to cover the access": Always reserve exactly the LR/SC access, and no more * "custom": Custom behavior, leading to an 'unpredictable' call on any LR/SC

sc_w/cp_custom_sc_addresses

Expected results

LRSC_FAIL_ON_NON_EXACT_LRSC

Whether or not a Store Conditional fails if its physical address and size do not exactly match the physical address and size of the last Load Reserved in program order (independent of whether or not the SC is in the current reservation set)

sc_d/cg_cp_custom_sc_lrsc, sc_w/cp_custom_sc_addresses

Expected results

LRSC_FAIL_ON_VA_SYNONYM

Whether or not an sc.l/sc.d will fail if its VA does not match the VA of the prior lr.l/lr.d, even if the physical address of the SC and LR are the same

Not tested because spec does not require any specific behavior

TODO: On implementations that support the C extension, compressed forms of the I instructions permitted inside constrained LR/SC sequences, as described in [sec:lrscseq], are also permitted.

A.7. Floating-Point Extensions

Supporting floating-point involves enabling at least the F extension. Other extensions depend on F. The coverpoints are specified in the following sections. Some tests only apply when multiple extensions are supported.

The basic coverpoints are defined in Table 9. Modified coverpoints for floating-point instructions are defined in Table 42. D and H suffixes apply to double-precision and half-precision floating-point instructions, respectively.

Table 42. Floating-Point Modified Coverpoint Definitions
Modified Coverpoint Bins Definition

cp_frm_{2, 3, 4}

6

Rounding modes for instructions with 2/3/4 arguments

cr_fs1_edges_frm

26 * 6

Cross product of fs1 edges and rounding modes

cp_csr_fflags_{n, v, vn, von, voun, vdoun}

2-10

Set / preserve fflags bits

cr_fs1_fs2_edges_frm

26 * 26 * 6

Cross product of fs1 and fs2 edges and rounding modes

cr_fs1_fs2_edges_frm4

26 * 26 * 6

Cross product of fs1 and fs2 edges and rounding modes for fma

cr_fs1_fs3_edges_frm4

26 * 26 * 6

Cross product of fs1 and fs3 edges and rounding modes for fma

These coverpoints do not yet certify that floating-point operations conform to the IEEE 754 standard. More robust coverpoints based on the IBM suite are under development.

A.7.1. F Single-Precision FP

Table 43. F Instruction Coverpoints
Instruction fadd.s fclass.s fcvt.l.s fcvt.lu.s fcvt.s.l fcvt.s.lu fcvt.s.w fcvt.s.wu fcvt.w.s

Type

FR

FIX

F2X

F2X

X2F

X2F

X2F

X2F

F2X

RV32

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_rs1

x

x

x

x

cp_rd

x

x

x

x

cp_rs1_edges

x

x

x

x

cp_fs1

x

x

x

x

x

cp_fs2

x

cp_fd

x

x

x

x

x

cp_fs1_edges

x

x

frm

frm

frm

cp_fs2_edges

x

cmp_fd_fs1

x

cmp_fd_fs2

x

cp_frm

3

2

2

2

2

2

2

2

cp_csr_fflags

von

vn

vn

n

n

n

n

vn

cp_csr_frm

x

x

x

x

x

x

x

x

cr_fs1_fs2_edges

frm

cp_fclass

x
Instruction fcvt.wu.s fdiv.s feq.s fle.s flt.s flw fmadd.s fmax.s fmin.s

Type

F2X

FR

FC

FC

FC

FL

FR4

FR

FR

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_rs1

nx0

cp_rd

x

x

x

x

cp_imm_edges

x

cp_fs1

x

x

x

x

x

x

x

x

cp_fs2

x

x

x

x

x

x

x

cp_fs3

x

cp_fd

x

x

x

x

x

cp_fs1_edges

frm

x

x

x

x

x

x

x

cp_fs2_edges

x

x

x

x

x

x

x

cp_fs3_edges

x

cmp_fd_fs1

x

x

x

x

cmp_fd_fs2

x

x

x

x

cmp_fd_fs3

x

cp_frm

2

3

4

cp_csr_fflags

vn

vdoun

v

v

v

voun

v

v

cp_csr_frm

x

x

x

cr_fs1_fs2_edges

frm

x

x

x

frm4

x

x

cr_fs1_fs3_edges

frm4
Instruction fmsub.s fmul.s fmv.w.x fmv.x.w fnmadd.s fnmsub.s fsgnj.s fsgnjn.s fsgnjx.s

Type

FR4

FR

X2F

F2X

FR4

FR4

FR

FR

FR

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_rs1

x

cp_rd

x

cp_rs1_edges

x

cp_fs1

x

x

x

x

x

x

x

x

cp_fs2

x

x

x

x

x

x

x

cp_fs3

x

x

x

cp_fd

x

x

x

x

x

x

x

x

cp_fs1_edges

x

x

x

x

x

x

x

x

cp_fs2_edges

x

x

x

x

x

x

x

cp_fs3_edges

x

x

x

cmp_fd_fs1

x

x

x

x

x

x

x

cmp_fd_fs2

x

x

x

x

x

x

x

cmp_fd_fs3

x

x

x

cp_frm

4

3

4

4

cp_csr_fflags

voun

voun

voun

voun

cp_csr_frm

x

x

x

x

cr_fs1_fs2_edges

frm4

frm

frm4

frm4

x

x

x

cr_fs1_fs3_edges

frm4

frm4

frm4
Instruction fsqrt.s fsub.s fsw

Type

FI

FR

FS

RV32

x

x

x

RV64

x

x

x

cp_asm_count

x

x

x

cp_rs1

nx0

cp_imm_edges

x

cp_fs1

x

x

cp_fs2

x

x

cp_fd

x

x

cp_fs1_edges

frm

x

cp_fs2_edges

x

x

cmp_fd_fs1

x

x

cmp_fd_fs2

x

cp_frm

2

3

cp_csr_fflags

vn

von

cp_csr_frm

x

x

cr_fs1_fs2_edges

frm
Table 44. F Normative Rules
Normative Rule Rule Text Coverpoints

fadd-s_op

FADD.S and FMUL.S perform single-precision floating-point addition and multiplication respectively, between rs1 and rs2 In each case, the result is written to rd. The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

F_fadd_s_cg/{cp_fs1, cp_fs2, cp_fd, cp_frm_3, cp_csr_fflags_von, cp_csr_frm, cr_fs1_fs2_edges_frm} TODO: Use IBM coverpoints on all FP tests regarding detecting tininess after rounding

fclass-s_op

The FCLASS.S instruction examines the value in floating-point register rs1 and writes to integer register rd a 10-bit mask that indicates the class of the floating-point number. The format of the mask is described in . The corresponding bit in rd will be set if the property is true and clear otherwise. All other bits in rd are cleared. Note that exactly one bit in rd will be set. FCLASS.S does not set the floating-point exception flags.

F_fclass_s_cg/{cp_rd, cp_fs1, cp_fs1_edges, cp_fclass}

fcvt-l-s_op

FCVT.W.S or FCVT.L.S converts a floating-point number in floating-point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. FCVT.L[U].S and FCVT.S.L[U] are RV64-only instructions The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. [int_conv] gives the range of valid inputs for FCVT.int.S and the behavior for invalid inputs All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

F_fcvt_l_s_cg/{cp_rd, cp_fs1, cp_fs1_edges_frm, cp_frm_2, cp_csr_fflags_vn, cp_csr_frm}

fcvt-lu-s_op

FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and FCVT.S.LU variants convert to or from unsigned integer values. For XLEN>32, FCVT.W[U].S sign-extends the 32-bit result to the destination register width All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. FCVT.L[U].S and FCVT.S.L[U] are RV64-only instructions [int_conv] gives the range of valid inputs for FCVT.int.S and the behavior for invalid inputs All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

F_fcvt_lu_s_cg/{cp_rd, cp_fs1, cp_fs1_edges_frm, cp_frm_2, cp_csr_fflags_vn, cp_csr_frm}

fcvt-s-l_op

FCVT.S.W or FCVT.S.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a floating-point number in floating-point register rd All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. FCVT.L[U].S and FCVT.S.L[U] are RV64-only instructions The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

F_fcvt_s_l_cg/{cp_rs1, cp_rs1_edges, cp_fd, cp_frm_2, cp_csr_fflags_n, cp_csr_frm}

fcvt-s-lu_op

FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and FCVT.S.LU variants convert to or from unsigned integer values. For XLEN>32, FCVT.W[U].S sign-extends the 32-bit result to the destination register width All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. FCVT.L[U].S and FCVT.S.L[U] are RV64-only instructions All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

F_fcvt_s_lu_cg/{cp_rs1, cp_rs1_edges, cp_fd, cp_frm_2, cp_csr_fflags_n, cp_csr_frm}

fcvt-s-w_op

FCVT.S.W or FCVT.S.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a floating-point number in floating-point register rd All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

F_fcvt_s_w_cg/{cp_rs1, cp_rs1_edges, cp_fd, cp_frm_2, cp_csr_fflags_n, cp_csr_frm}

fcvt-s-wu_op

FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and FCVT.S.LU variants convert to or from unsigned integer values. For XLEN>32, FCVT.W[U].S sign-extends the 32-bit result to the destination register width All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

F_fcvt_s_wu_cg/{cp_rs1, cp_rs1_edges, cp_fd, cp_frm_2, cp_csr_fflags_n, cp_csr_frm}

fcvt-w-s_op

FCVT.W.S or FCVT.L.S converts a floating-point number in floating-point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. [int_conv] gives the range of valid inputs for FCVT.int.S and the behavior for invalid inputs All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

F_fcvt_w_s_cg/{cp_rd, cp_fs1, cp_fs1_edges_frm, cp_frm_2, cp_csr_fflags_vn, cp_csr_frm}

fcvt-wu-s_op

FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and FCVT.S.LU variants convert to or from unsigned integer values. For XLEN>32, FCVT.W[U].S sign-extends the 32-bit result to the destination register width All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. [int_conv] gives the range of valid inputs for FCVT.int.S and the behavior for invalid inputs All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

F_fcvt_wu_s_cg/{cp_rd, cp_fs1, cp_fs1_edges_frm, cp_frm_2, cp_csr_fflags_vn, cp_csr_frm}

fdiv-s_op

FDIV.S performs the single-precision floating-point division of rs1 by rs2 In each case, the result is written to rd. The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

F_fdiv_s_cg/{cp_fs1, cp_fs2, cp_fd, cp_frm_3, cp_csr_fflags_vdoun, cp_csr_frm, cr_fs1_fs2_edges_frm}

feq-s_op

Floating-point compare instructions (FEQ.S, FLT.S, FLE.S) perform the specified comparison between floating-point registers (rs1 = rs2, rs1 < rs2, rs1 ≤ rs2) writing 1 to the integer register rd if the condition holds, and 0 otherwise.

F_feq_s_cg/{cp_rd, cp_fs1, cp_fs2, cp_csr_fflags_v, cr_fs1_fs2_edges}

fle-s_op

Floating-point compare instructions (FEQ.S, FLT.S, FLE.S) perform the specified comparison between floating-point registers (rs1 = rs2, rs1 < rs2, rs1 ≤ rs2) writing 1 to the integer register rd if the condition holds, and 0 otherwise.

F_fle_s_cg/{cp_rd, cp_fs1, cp_fs2, cp_csr_fflags_v, cr_fs1_fs2_edges}

flt-s_op

Floating-point compare instructions (FEQ.S, FLT.S, FLE.S) perform the specified comparison between floating-point registers (rs1 = rs2, rs1 < rs2, rs1 ≤ rs2) writing 1 to the integer register rd if the condition holds, and 0 otherwise.

F_flt_s_cg/{cp_rd, cp_fs1, cp_fs2, cp_csr_fflags_v, cr_fs1_fs2_edges}

flw_op

Floating-point loads and stores use the same base+offset addressing mode as the integer base ISAs, with a base address in register rs1 and a 12-bit signed byte offset. The FLW instruction loads a single-precision floating-point value from memory into floating-point register rd. FSW stores a single-precision value from floating-point register rs2 to memory.

F_flw_cg/{cp_rs1_nx0, cp_imm_edges, cp_fd}

fmadd-s_op

FMADD.S multiplies the values in rs1 and rs2, adds the value in rs3, and writes the final result to rd. FMADD.S computes (rs1×rs2)+rs3. Floating-point fused multiply-add instructions require a new standard instruction format. R4-type instructions specify three source registers (rs1, rs2, and rs3) and a destination register (rd). This format is only used by the floating-point fused multiply-add instructions. The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. The fused multiply-add instructions must set the invalid operation exception flag when the multiplicands are ∞ and zero, even when the addend is a quiet NaN. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

F_fmadd_s_cg/{cp_fs1, cp_fs2, cp_fs3, cp_fd, cp_frm_4, cp_csr_fflags_voun, cp_csr_frm, cr_fs1_fs2_edges_frm4, cr_fs1_fs3_edges_frm4}

fmax-s_op

Floating-point minimum-number and maximum-number instructions FMIN.S and FMAX.S write, respectively, the smaller or larger of rs1 and rs2 to rd

F_fmax_s_cg/{cp_fs1, cp_fs2, cp_fd, cp_csr_fflags_v, cr_fs1_fs2_edges}

fmin-s_op

Floating-point minimum-number and maximum-number instructions FMIN.S and FMAX.S write, respectively, the smaller or larger of rs1 and rs2 to rd

F_fmin_s_cg/{cp_fs1, cp_fs2, cp_fd, cp_csr_fflags_v, cr_fs1_fs2_edges}

fmsub-s_op

FMSUB.S multiplies the values in rs1 and rs2, subtracts the value in rs3, and writes the final result to rd. FMSUB.S computes (rs1×rs2)−rs3. Floating-point fused multiply-add instructions require a new standard instruction format. R4-type instructions specify three source registers (rs1, rs2, and rs3) and a destination register (rd). This format is only used by the floating-point fused multiply-add instructions. The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. The fused multiply-add instructions must set the invalid operation exception flag when the multiplicands are ∞ and zero, even when the addend is a quiet NaN. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

F_fmsub_s_cg/{cp_fs1, cp_fs2, cp_fs3, cp_fd, cp_frm_4, cp_csr_fflags_voun, cp_csr_frm, cr_fs1_fs2_edges_frm4, cr_fs1_fs3_edges_frm4}

fmul-s_op

FADD.S and FMUL.S perform single-precision floating-point addition and multiplication respectively, between rs1 and rs2 In each case, the result is written to rd. The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

F_fmul_s_cg/{cp_fs1, cp_fs2, cp_fd, cp_frm_3, cp_csr_fflags_voun, cp_csr_frm, cr_fs1_fs2_edges_frm}

fmv-w-x_op

FMV.W.X moves the single-precision value encoded in IEEE 754-2008 standard encoding from the lower 32 bits of integer register rs1 to the floating-point register rd. The bits are not modified in the transfer, and in particular, the payloads of non-canonical NaNs are preserved.

F_fmv_w_x_cg/{cp_rs1, cp_rs1_edges, cp_fd}

fmv-x-w_op

FMV.X.W moves the single-precision value in floating-point register rs1 represented in IEEE 754-2008 encoding to the lower 32 bits of integer register rd. The bits are not modified in the transfer, and in particular, the payloads of non-canonical NaNs are preserved. For RV64, the higher 32 bits of the destination register are filled with copies of the floating-point number’s sign bit

F_fmv_x_w_cg/{cp_rd, cp_fs1, cp_fs1_edges}

fnmadd-s_op

FNMADD.S multiplies the values in rs1 and rs2, negates the product, subtracts the value in rs3, and writes the final result to rd. FNMADD.S computes −(rs1×rs2)−rs3. Floating-point fused multiply-add instructions require a new standard instruction format. R4-type instructions specify three source registers (rs1, rs2, and rs3) and a destination register (rd). This format is only used by the floating-point fused multiply-add instructions. The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. The fused multiply-add instructions must set the invalid operation exception flag when the multiplicands are ∞ and zero, even when the addend is a quiet NaN. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

F_fnmadd_s_cg/{cp_fs1, cp_fs2, cp_fs3, cp_fd, cp_frm_4, cp_csr_fflags_voun, cp_csr_frm, cr_fs1_fs2_edges_frm4, cr_fs1_fs3_edges_frm4}

fnmsub-s_op

FNMSUB.S multiplies the values in rs1 and rs2, negates the product, adds the value in rs3, and writes the final result to rd. FNMSUB.S computes −(rs1×rs2)+rs3. Floating-point fused multiply-add instructions require a new standard instruction format. R4-type instructions specify three source registers (rs1, rs2, and rs3) and a destination register (rd). This format is only used by the floating-point fused multiply-add instructions. The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. The fused multiply-add instructions must set the invalid operation exception flag when the multiplicands are ∞ and zero, even when the addend is a quiet NaN. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

F_fnmsub_s_cg/{cp_fs1, cp_fs2, cp_fs3, cp_fd, cp_frm_4, cp_csr_fflags_voun, cp_csr_frm, cr_fs1_fs2_edges_frm4, cr_fs1_fs3_edges_frm4}

fsgnj-s_op

Floating-point to floating-point sign-injection instructions, FSGNJ.S, FSGNJN.S, and FSGNJX.S, produce a result that takes all bits except the sign bit from rs1. For FSGNJ, the result’s sign bit is rs2’s sign bit; for FSGNJN, the result’s sign bit is the opposite of rs2’s sign bit; and for FSGNJX, the sign bit is the XOR of the sign bits of rs1 and rs2. Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension.

F_fsgnj_s_cg/{cp_fs1, cp_fs2, cp_fd, cr_fs1_fs2_edges}

fsgnjn-s_op

Floating-point to floating-point sign-injection instructions, FSGNJ.S, FSGNJN.S, and FSGNJX.S, produce a result that takes all bits except the sign bit from rs1. For FSGNJ, the result’s sign bit is rs2’s sign bit; for FSGNJN, the result’s sign bit is the opposite of rs2’s sign bit; and for FSGNJX, the sign bit is the XOR of the sign bits of rs1 and rs2. Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension.

F_fsgnjn_s_cg/{cp_fs1, cp_fs2, cp_fd, cr_fs1_fs2_edges}

fsgnjx-s_op

Floating-point to floating-point sign-injection instructions, FSGNJ.S, FSGNJN.S, and FSGNJX.S, produce a result that takes all bits except the sign bit from rs1. For FSGNJ, the result’s sign bit is rs2’s sign bit; for FSGNJN, the result’s sign bit is the opposite of rs2’s sign bit; and for FSGNJX, the sign bit is the XOR of the sign bits of rs1 and rs2. Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension.

F_fsgnjx_s_cg/{cp_fs1, cp_fs2, cp_fd, cr_fs1_fs2_edges}

fsqrt-s_op

FSQRT.S computes the square root of rs1 In each case, the result is written to rd. The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

F_fsqrt_s_cg/{cp_fs1, cp_fd, cp_fs1_edges, cp_frm_2, cp_csr_fflags_vn, cp_csr_frm}

fsub-s_op

FSUB.S performs the single-precision floating-point subtraction of rs2 from rs1 In each case, the result is written to rd. The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

F_fsub_s_cg/{cp_fs1, cp_fs2, cp_fd, cp_frm_3, cp_csr_fflags_von, cp_csr_frm, cr_fs1_fs2_edges_frm}

fsw_op

Floating-point loads and stores use the same base+offset addressing mode as the integer base ISAs, with a base address in register rs1 and a 12-bit signed byte offset. The FLW instruction loads a single-precision floating-point value from memory into floating-point register rd. FSW stores a single-precision value from floating-point register rs2 to memory.

F_fsw_cg/{cp_rs1_nx0, cp_imm_edges, cp_fs2, cp_fs2_edges}

UDB Parameters: None.

A.7.2. D Double-Precision FP

Table 45. D Instruction Coverpoints
Instruction fadd.d fclass.d fcvt.d.l fcvt.d.lu fcvt.d.s fcvt.d.w fcvt.d.wu fcvt.l.d fcvt.lu.d

Type

FR

FIX

X2F

X2F

FI

X2F

X2F

F2X

F2X

RV32

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_rs1

x

x

x

x

cp_rd

x

x

x

cp_rs1_edges

x

x

x

x

cp_fs1

x

x

x

x

x

cp_fs2

x

cp_fd

x

x

x

x

x

x

cp_fs1_edges

D

D

x

frm_D

frm_D

cp_fs2_edges

D

cmp_fd_fs1

x

x

cmp_fd_fs2

x

cp_frm

3

2

2

2

2

cp_csr_fflags

von

n

n

v

vn

vn

cp_csr_frm

x

x

x

x

x

cr_fs1_fs2_edges

frm_D

cp_fclass

x

cp_fs1_badNB

D_S
Instruction fcvt.s.d fcvt.w.d fcvt.wu.d fdiv.d feq.d fld fle.d flt.d fmadd.d

Type

FI

F2X

F2X

FR

FC

FL

FC

FC

FR4

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_rs1

nx0

cp_rd

x

x

x

x

x

cp_imm_edges

x

cp_fs1

x

x

x

x

x

x

x

x

cp_fs2

x

x

x

x

x

cp_fs3

x

cp_fd

x

x

x

x

cp_fs1_edges

frm_D

frm_D

frm_D

D

D

D

D

D

cp_fs2_edges

D

D

D

D

D

cp_fs3_edges

D

cmp_fd_fs1

x

x

x

cmp_fd_fs2

x

x

cmp_fd_fs3

x

cp_frm

2

2

2

3

4

cp_csr_fflags

voun

vn

vn

vdoun

v

v

v

voun

cp_csr_frm

x

x

x

x

x

cr_fs1_fs2_edges

frm_D

D

D

D

frm4_D

cr_fs1_fs3_edges

frm4_D

cp_NaNBox

D_S
Instruction fmax.d fmin.d fmsub.d fmul.d fmv.d.x fmv.x.d fnmadd.d fnmsub.d fsd

Type

FR

FR

FR4

FR

X2F

F2X

FR4

FR4

FS

RV32

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_rs1

x

nx0

cp_rd

x

cp_rs1_edges

x

cp_imm_edges

x

cp_fs1

x

x

x

x

x

x

x

cp_fs2

x

x

x

x

x

x

x

cp_fs3

x

x

x

cp_fd

x

x

x

x

x

x

x

cp_fs1_edges

D

D

D

D

D

D

D

cp_fs2_edges

D

D

D

D

D

D

x

cp_fs3_edges

D

D

D

cmp_fd_fs1

x

x

x

x

x

x

cmp_fd_fs2

x

x

x

x

x

x

cmp_fd_fs3

x

x

x

cp_frm

4

3

4

4

cp_csr_fflags

v

v

voun

voun

voun

voun

cp_csr_frm

x

x

x

x

cr_fs1_fs2_edges

D

D

frm4_D

frm_D

frm4_D

frm4_D

cr_fs1_fs3_edges

frm4_D

frm4_D

frm4_D
Instruction fsgnj.d fsgnjn.d fsgnjx.d fsqrt.d fsub.d

Type

FR

FR

FR

FI

FR

RV32

x

x

x

x

x

RV64

x

x

x

x

x

cp_asm_count

x

x

x

x

x

cp_fs1

x

x

x

x

x

cp_fs2

x

x

x

x

cp_fd

x

x

x

x

x

cp_fs1_edges

D

D

D

D

D

cp_fs2_edges

D

D

D

D

cmp_fd_fs1

x

x

x

x

x

cmp_fd_fs2

x

x

x

x

cp_frm

2

3

cp_csr_fflags

vn

von

cp_csr_frm

x

x

cr_fs1_fs2_edges

D

D

D

frm_D
Instruction fadd.s fclass.s fcvt.l.s fcvt.lu.s fcvt.s.l fcvt.s.lu fcvt.s.w fcvt.s.wu fcvt.w.s

Type

FR

FIX

F2X

F2X

X2F

X2F

X2F

X2F

F2X

RV32

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

cp_NaNBox

D_S

D_S

D_S

D_S

D_S

cp_fs1_badNB

D_S

D_S

D_S

D_S

D_S

cp_fs2_badNB

D_S
Instruction fcvt.wu.s fdiv.s feq.s fle.s flt.s flw fmadd.s fmax.s fmin.s

Type

F2X

FR

FC

FC

FC

FL

FR4

FR

FR

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

cp_NaNBox

D_S

D_S

D_S

D_S

D_S

cp_fs1_badNB

D_S

D_S

D_S

D_S

D_S

D_S

D_S

D_S

cp_fs2_badNB

D_S

D_S

D_S

D_S

D_S

D_S

D_S

cp_fs3_badNB

D_S
Instruction fmsub.s fmul.s fmv.w.x fmv.x.w fnmadd.s fnmsub.s fsgnj.s fsgnjn.s fsgnjx.s

Type

FR4

FR

X2F

F2X

FR4

FR4

FR

FR

FR

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

cp_NaNBox

D_S

D_S

D_S

D_S

D_S

D_S

D_S

D_S

cp_fs1_badNB

D_S

D_S

D_S

D_S

D_S

D_S

D_S

D_S

cp_fs2_badNB

D_S

D_S

D_S

D_S

D_S

D_S

D_S

cp_fs3_badNB

D_S

D_S

D_S
Instruction fsqrt.s fsub.s fsw

Type

FI

FR

FS

RV32

x

x

x

RV64

x

x

x

cp_NaNBox

D_S

D_S

cp_fs1_badNB

D_S

D_S

cp_fs2_badNB

D_S

D_S
Table 46. D Normative Rules
Normative Rule Rule Text Coverpoints

D_fpr_regs

The F extension adds 32 floating-point registers, f0-f31, each 32 bits wide The D extension widens the 32 floating-point registers, f0-f31, to 64 bits (FLEN=64 in [fprs]

D_fadd_d_cg/{cp_fs1_fs2_edges_frm_D}

fsd_atomic_align, fld_atomic_align

FLD and FSD are only guaranteed to execute atomically if the effective address is naturally aligned and XLEN≥64.

UNCHECKED

fsd_bits_maintained

FLD and FSD do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.

TODO

fld_bits_maintained

FLD and FSD do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.

TODO

fmv-x-d_op_bits_preserved

FMV.X.D and FMV.D.X do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.

fmv-d-x_op_bits_preserved

FMV.X.D and FMV.D.X do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.

feq-d_NaN

For all three instructions, the result is 0 if either operand is NaN FEQ.S performs a quiet comparison: it only sets the invalid operation exception flag if either input is a signaling NaN The double-precision floating-point compare instructions are defined analogously to their single-precision counterparts, but operate on double-precision operands.

flt-d_NaN

For all three instructions, the result is 0 if either operand is NaN FLT.S and FLE.S perform what the IEEE 754-2008 standard refers to as signaling comparisons: that is, they set the invalid operation exception flag if either input is NaN The double-precision floating-point compare instructions are defined analogously to their single-precision counterparts, but operate on double-precision operands.

fle-d_NaN

For all three instructions, the result is 0 if either operand is NaN FLT.S and FLE.S perform what the IEEE 754-2008 standard refers to as signaling comparisons: that is, they set the invalid operation exception flag if either input is NaN The double-precision floating-point compare instructions are defined analogously to their single-precision counterparts, but operate on double-precision operands.

fp_nan-boxing

When multiple floating-point precisions are supported, then valid values of narrower n-bit types, n<FLEN, are represented in the lower n bits of an FLEN-bit NaN value, in a process termed NaN-boxing. The upper bits of a valid NaN-boxed value must be all 1s. Valid NaN-boxed n-bit values therefore appear as negative quiet NaNs (qNaNs) when viewed as any wider m-bit value, n < m ≤ FLEN. Any operation that writes a narrower result to an 'f' register must write all 1s to the uppermost FLEN-n bits to yield a legal NaN-boxedvalue.

FP_transfer_instrs_narrow_transfer_in

A narrower n-bit transfer, n<FLEN, into the f registers will create a valid NaN-boxed value

FP_transfer_instrs_narrow_transfer_out

A narrower n-bit transfer out of the floating-point registers will transfer the lower n bits of the register ignoring the upper FLEN-n bits

fcvt-w-d_fcvt-wu-d_sign_ext

For RV64, FCVT.W[U].D sign-extends the 32-bit result

fadd-d_op

FADD.S and FMUL.S perform single-precision floating-point addition and multiplication respectively, between rs1 and rs2 The double-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on double-precision operands and produce double-precision results. Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

D_fadd_d_cg/{cp_fs1, cp_fs2, cp_fd, cp_frm_3, cp_csr_fflags_von, cp_csr_frm, cr_fs1_fs2_edges_frm_D}

fclass-d_op

The FCLASS.S instruction examines the value in floating-point register rs1 and writes to integer register rd a 10-bit mask that indicates the class of the floating-point number. The format of the mask is described in . The corresponding bit in rd will be set if the property is true and clear otherwise. All other bits in rd are cleared. Note that exactly one bit in rd will be set. FCLASS.S does not set the floating-point exception flags. The double-precision floating-point classify instruction, FCLASS.D, is defined analogously to its single-precision counterpart, but operates on double-precision operands.

D_fclass_d_cg/{cp_rd, cp_fs1, cp_fs1_edges_D, cp_fclass}

fcvt-d-l_op

FCVT.D.W or FCVT.D.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a double-precision floating-point number in floating-point register rd All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. FCVT.L[U].D and FCVT.D.L[U] are RV64-only instructions. All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

D_fcvt_d_l_cg/{cp_rs1, cp_rs1_edges, cp_fd, cp_frm_2, cp_csr_fflags_n, cp_csr_frm}

fcvt-d-lu_op

FCVT.WU.D, FCVT.LU.D, FCVT.D.WU, and FCVT.D.LU variants convert to or from unsigned integer values All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. FCVT.L[U].D and FCVT.D.L[U] are RV64-only instructions. All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

D_fcvt_d_lu_cg/{cp_rs1, cp_rs1_edges, cp_fd, cp_frm_2, cp_csr_fflags_n, cp_csr_frm}

fcvt-d-s_op

The double-precision to single-precision and single-precision to double-precision conversion instructions, FCVT.S.D and FCVT.D.S, are encoded in the OP-FP major opcode space and both the source and destination are floating-point registers. The rs2 field encodes the datatype of the source, and the fmt field encodes the datatype of the destination FCVT.S.D rounds according to the RM field; FCVT.D.S will never round

D_fcvt_d_s_cg/{cp_fs1, cp_fd, cp_fs1_edges, cp_csr_fflags_v, cp_fs1_badNB_D_S}

fcvt-d-w_op

FCVT.D.W or FCVT.D.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a double-precision floating-point number in floating-point register rd All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

D_fcvt_d_w_cg/{cp_rs1, cp_rs1_edges, cp_fd}

fcvt-d-wu_op

FCVT.WU.D, FCVT.LU.D, FCVT.D.WU, and FCVT.D.LU variants convert to or from unsigned integer values All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

D_fcvt_d_wu_cg/{cp_rs1, cp_rs1_edges, cp_fd}

fcvt-l-d_op

FCVT.W.D or FCVT.L.D converts a double-precision floating-point number in floating-point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. FCVT.L[U].D and FCVT.D.L[U] are RV64-only instructions. The range of valid inputs for FCVT.int.D and the behavior for invalid inputs are the same as for FCVT.int.S All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

D_fcvt_l_d_cg/{cp_rd, cp_fs1, cp_fs1_edges_frm_D, cp_frm_2, cp_csr_fflags_vn, cp_csr_frm}

fcvt-lu-d_op

FCVT.WU.D, FCVT.LU.D, FCVT.D.WU, and FCVT.D.LU variants convert to or from unsigned integer values All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. FCVT.L[U].D and FCVT.D.L[U] are RV64-only instructions. The range of valid inputs for FCVT.int.D and the behavior for invalid inputs are the same as for FCVT.int.S All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

D_fcvt_lu_d_cg/{cp_rd, cp_fs1, cp_fs1_edges_frm_D, cp_frm_2, cp_csr_fflags_vn, cp_csr_frm}

fcvt-s-d_op

The double-precision to single-precision and single-precision to double-precision conversion instructions, FCVT.S.D and FCVT.D.S, are encoded in the OP-FP major opcode space and both the source and destination are floating-point registers. The rs2 field encodes the datatype of the source, and the fmt field encodes the datatype of the destination FCVT.S.D rounds according to the RM field; FCVT.D.S will never round

D_fcvt_s_d_cg/{cp_fs1, cp_fd, cp_fs1_edges_frm_D, cp_frm_2, cp_csr_fflags_voun, cp_csr_frm, cp_NaNBox_D_S}

fcvt-w-d_op

FCVT.W.D or FCVT.L.D converts a double-precision floating-point number in floating-point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. The range of valid inputs for FCVT.int.D and the behavior for invalid inputs are the same as for FCVT.int.S All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

D_fcvt_w_d_cg/{cp_rd, cp_fs1, cp_fs1_edges_frm_D, cp_frm_2, cp_csr_fflags_vn, cp_csr_frm}

fcvt-wu-d_op

FCVT.WU.D, FCVT.LU.D, FCVT.D.WU, and FCVT.D.LU variants convert to or from unsigned integer values All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. The range of valid inputs for FCVT.int.D and the behavior for invalid inputs are the same as for FCVT.int.S All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

D_fcvt_wu_d_cg/{cp_rd, cp_fs1, cp_fs1_edges_frm_D, cp_frm_2, cp_csr_fflags_vn, cp_csr_frm}

fdiv-d_op

FDIV.S performs the single-precision floating-point division of rs1 by rs2 The double-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on double-precision operands and produce double-precision results. Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

D_fdiv_d_cg/{cp_fs1, cp_fs2, cp_fd, cp_frm_3, cp_csr_fflags_vdoun, cp_csr_frm, cr_fs1_fs2_edges_frm_D}

feq-d_op

Floating-point compare instructions (FEQ.S, FLT.S, FLE.S) perform the specified comparison between floating-point registers (rs1 = rs2, rs1 < rs2, rs1 ≤ rs2) writing 1 to the integer register rd if the condition holds, and 0 otherwise. The double-precision floating-point compare instructions are defined analogously to their single-precision counterparts, but operate on double-precision operands.

D_feq_d_cg/{cp_rd, cp_fs1, cp_fs2, cp_csr_fflags_v, cr_fs1_fs2_edges_D}

fld_op

The FLD instruction loads a double-precision floating-point value from memory into floating-point register rd

D_fld_cg/{cp_rs1_nx0, cp_imm_edges, cp_fd}

fle-d_op

Floating-point compare instructions (FEQ.S, FLT.S, FLE.S) perform the specified comparison between floating-point registers (rs1 = rs2, rs1 < rs2, rs1 ≤ rs2) writing 1 to the integer register rd if the condition holds, and 0 otherwise. The double-precision floating-point compare instructions are defined analogously to their single-precision counterparts, but operate on double-precision operands.

D_fle_d_cg/{cp_rd, cp_fs1, cp_fs2, cp_csr_fflags_v, cr_fs1_fs2_edges_D}

flt-d_op

Floating-point compare instructions (FEQ.S, FLT.S, FLE.S) perform the specified comparison between floating-point registers (rs1 = rs2, rs1 < rs2, rs1 ≤ rs2) writing 1 to the integer register rd if the condition holds, and 0 otherwise. The double-precision floating-point compare instructions are defined analogously to their single-precision counterparts, but operate on double-precision operands.

D_flt_d_cg/{cp_rd, cp_fs1, cp_fs2, cp_csr_fflags_v, cr_fs1_fs2_edges_D}

fmadd-d_op

FMADD.S multiplies the values in rs1 and rs2, adds the value in rs3, and writes the final result to rd. FMADD.S computes (rs1×rs2)+rs3. The double-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on double-precision operands and produce double-precision results. Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. The fused multiply-add instructions must set the invalid operation exception flag when the multiplicands are ∞ and zero, even when the addend is a quiet NaN. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

D_fmadd_d_cg/{cp_fs1, cp_fs2, cp_fs3, cp_fd, cp_frm_4, cp_csr_fflags_voun, cp_csr_frm, cr_fs1_fs2_edges_frm4_D, cr_fs1_fs3_edges_frm4_D}

fmsub-d_op

FMSUB.S multiplies the values in rs1 and rs2, subtracts the value in rs3, and writes the final result to rd. FMSUB.S computes (rs1×rs2)−rs3. The double-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on double-precision operands and produce double-precision results. Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. The fused multiply-add instructions must set the invalid operation exception flag when the multiplicands are ∞ and zero, even when the addend is a quiet NaN. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

D_fmsub_d_cg/{cp_fs1, cp_fs2, cp_fs3, cp_fd, cp_frm_4, cp_csr_fflags_voun, cp_csr_frm, cr_fs1_fs2_edges_frm4_D, cr_fs1_fs3_edges_frm4_D}

fmul-d_op

FADD.S and FMUL.S perform single-precision floating-point addition and multiplication respectively, between rs1 and rs2 The double-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on double-precision operands and produce double-precision results. Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

D_fmul_d_cg/{cp_fs1, cp_fs2, cp_fd, cp_frm_3, cp_csr_fflags_voun, cp_csr_frm, cr_fs1_fs2_edges_frm_D}

fmv-d-x_op

FMV.D.X moves the double-precision value encoded in IEEE 754-2008 standard encoding from the integer register rs1 to the floating-point register rd

D_fmv_d_x_cg/{cp_rs1, cp_rs1_edges, cp_fd}

fmv-x-d_op

FMV.X.D moves the double-precision value in floating-point register rs1 to a representation in IEEE 754-2008 standard encoding in integer register rd

D_fmv_x_d_cg/{cp_rd, cp_fs1, cp_fs1_edges_D}

fnmadd-d_op

FNMADD.S multiplies the values in rs1 and rs2, negates the product, subtracts the value in rs3, and writes the final result to rd. FNMADD.S computes −(rs1×rs2)−rs3. The double-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on double-precision operands and produce double-precision results. Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. The fused multiply-add instructions must set the invalid operation exception flag when the multiplicands are ∞ and zero, even when the addend is a quiet NaN. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

D_fnmadd_d_cg/{cp_fs1, cp_fs2, cp_fs3, cp_fd, cp_frm_4, cp_csr_fflags_voun, cp_csr_frm, cr_fs1_fs2_edges_frm4_D, cr_fs1_fs3_edges_frm4_D}

fnmsub-d_op

FNMSUB.S multiplies the values in rs1 and rs2, negates the product, adds the value in rs3, and writes the final result to rd. FNMSUB.S computes −(rs1×rs2)+rs3. The double-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on double-precision operands and produce double-precision results. Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. The fused multiply-add instructions must set the invalid operation exception flag when the multiplicands are ∞ and zero, even when the addend is a quiet NaN. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

D_fnmsub_d_cg/{cp_fs1, cp_fs2, cp_fs3, cp_fd, cp_frm_4, cp_csr_fflags_voun, cp_csr_frm, cr_fs1_fs2_edges_frm4_D, cr_fs1_fs3_edges_frm4_D}

fsd_op

FSD stores a double-precision value from the floating-point registers to memory

D_fsd_cg/{cp_rs1_nx0, cp_imm_edges, cp_fs2, cp_fs2_edges}

fsgnj-d_op

Floating-point to floating-point sign-injection instructions, FSGNJ.S, FSGNJN.S, and FSGNJX.S, produce a result that takes all bits except the sign bit from rs1. For FSGNJ, the result’s sign bit is rs2’s sign bit; for FSGNJN, the result’s sign bit is the opposite of rs2’s sign bit; and for FSGNJX, the sign bit is the XOR of the sign bits of rs1 and rs2. Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs Floating-point to floating-point sign-injection instructions, FSGNJ.D, FSGNJN.D, and FSGNJX.D are defined analogously to the single-precision sign-injection instruction.

D_fsgnj_d_cg/{cp_fs1, cp_fs2, cp_fd, cr_fs1_fs2_edges_D}

fsgnjn-d_op

Floating-point to floating-point sign-injection instructions, FSGNJ.S, FSGNJN.S, and FSGNJX.S, produce a result that takes all bits except the sign bit from rs1. For FSGNJ, the result’s sign bit is rs2’s sign bit; for FSGNJN, the result’s sign bit is the opposite of rs2’s sign bit; and for FSGNJX, the sign bit is the XOR of the sign bits of rs1 and rs2. Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs Floating-point to floating-point sign-injection instructions, FSGNJ.D, FSGNJN.D, and FSGNJX.D are defined analogously to the single-precision sign-injection instruction.

D_fsgnjn_d_cg/{cp_fs1, cp_fs2, cp_fd, cr_fs1_fs2_edges_D}

fsgnjx-d_op

Floating-point to floating-point sign-injection instructions, FSGNJ.S, FSGNJN.S, and FSGNJX.S, produce a result that takes all bits except the sign bit from rs1. For FSGNJ, the result’s sign bit is rs2’s sign bit; for FSGNJN, the result’s sign bit is the opposite of rs2’s sign bit; and for FSGNJX, the sign bit is the XOR of the sign bits of rs1 and rs2. Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs Floating-point to floating-point sign-injection instructions, FSGNJ.D, FSGNJN.D, and FSGNJX.D are defined analogously to the single-precision sign-injection instruction.

D_fsgnjx_d_cg/{cp_fs1, cp_fs2, cp_fd, cr_fs1_fs2_edges_D}

fsqrt-d_op

FSQRT.S computes the square root of rs1 The double-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on double-precision operands and produce double-precision results. Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

D_fsqrt_d_cg/{cp_fs1, cp_fd, cp_fs1_edges_D, cp_frm_2, cp_csr_fflags_vn, cp_csr_frm}

fsub-d_op

FSUB.S performs the single-precision floating-point subtraction of rs2 from rs1 The double-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on double-precision operands and produce double-precision results. Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

D_fsub_d_cg/{cp_fs1, cp_fs2, cp_fd, cp_frm_3, cp_csr_fflags_von, cp_csr_frm, cr_fs1_fs2_edges_frm_D}

fadd-s_op

FADD.S and FMUL.S perform single-precision floating-point addition and multiplication respectively, between rs1 and rs2 In each case, the result is written to rd. The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

D_fadd_s_cg/{cp_NaNBox_D_S, cp_fs1_badNB_D_S, cp_fs2_badNB_D_S}

fclass-s_op

The FCLASS.S instruction examines the value in floating-point register rs1 and writes to integer register rd a 10-bit mask that indicates the class of the floating-point number. The format of the mask is described in . The corresponding bit in rd will be set if the property is true and clear otherwise. All other bits in rd are cleared. Note that exactly one bit in rd will be set. FCLASS.S does not set the floating-point exception flags.

D_fclass_s_cg/{cp_fs1_badNB_D_S}

fcvt-l-s_op

FCVT.W.S or FCVT.L.S converts a floating-point number in floating-point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. FCVT.L[U].S and FCVT.S.L[U] are RV64-only instructions The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. [int_conv] gives the range of valid inputs for FCVT.int.S and the behavior for invalid inputs All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

D_fcvt_l_s_cg/{cp_fs1_badNB_D_S}

fcvt-lu-s_op

FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and FCVT.S.LU variants convert to or from unsigned integer values. For XLEN>32, FCVT.W[U].S sign-extends the 32-bit result to the destination register width All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. FCVT.L[U].S and FCVT.S.L[U] are RV64-only instructions [int_conv] gives the range of valid inputs for FCVT.int.S and the behavior for invalid inputs All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

D_fcvt_lu_s_cg/{cp_fs1_badNB_D_S}

fcvt-s-l_op

FCVT.S.W or FCVT.S.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a floating-point number in floating-point register rd All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. FCVT.L[U].S and FCVT.S.L[U] are RV64-only instructions The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

D_fcvt_s_l_cg/{cp_NaNBox_D_S}

fcvt-s-lu_op

FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and FCVT.S.LU variants convert to or from unsigned integer values. For XLEN>32, FCVT.W[U].S sign-extends the 32-bit result to the destination register width All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. FCVT.L[U].S and FCVT.S.L[U] are RV64-only instructions All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

D_fcvt_s_lu_cg/{cp_NaNBox_D_S}

fcvt-s-w_op

FCVT.S.W or FCVT.S.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a floating-point number in floating-point register rd All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

D_fcvt_s_w_cg/{cp_NaNBox_D_S}

fcvt-s-wu_op

FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and FCVT.S.LU variants convert to or from unsigned integer values. For XLEN>32, FCVT.W[U].S sign-extends the 32-bit result to the destination register width All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

D_fcvt_s_wu_cg/{cp_NaNBox_D_S}

fcvt-w-s_op

FCVT.W.S or FCVT.L.S converts a floating-point number in floating-point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. [int_conv] gives the range of valid inputs for FCVT.int.S and the behavior for invalid inputs All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

D_fcvt_w_s_cg/{cp_fs1_badNB_D_S}

fcvt-wu-s_op

FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and FCVT.S.LU variants convert to or from unsigned integer values. For XLEN>32, FCVT.W[U].S sign-extends the 32-bit result to the destination register width All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. [int_conv] gives the range of valid inputs for FCVT.int.S and the behavior for invalid inputs All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

D_fcvt_wu_s_cg/{cp_fs1_badNB_D_S}

fdiv-s_op

FDIV.S performs the single-precision floating-point division of rs1 by rs2 In each case, the result is written to rd. The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

D_fdiv_s_cg/{cp_NaNBox_D_S, cp_fs1_badNB_D_S, cp_fs2_badNB_D_S}

feq-s_op

Floating-point compare instructions (FEQ.S, FLT.S, FLE.S) perform the specified comparison between floating-point registers (rs1 = rs2, rs1 < rs2, rs1 ≤ rs2) writing 1 to the integer register rd if the condition holds, and 0 otherwise.

D_feq_s_cg/{cp_fs1_badNB_D_S, cp_fs2_badNB_D_S}

fle-s_op

Floating-point compare instructions (FEQ.S, FLT.S, FLE.S) perform the specified comparison between floating-point registers (rs1 = rs2, rs1 < rs2, rs1 ≤ rs2) writing 1 to the integer register rd if the condition holds, and 0 otherwise.

D_fle_s_cg/{cp_fs1_badNB_D_S, cp_fs2_badNB_D_S}

flt-s_op

Floating-point compare instructions (FEQ.S, FLT.S, FLE.S) perform the specified comparison between floating-point registers (rs1 = rs2, rs1 < rs2, rs1 ≤ rs2) writing 1 to the integer register rd if the condition holds, and 0 otherwise.

D_flt_s_cg/{cp_fs1_badNB_D_S, cp_fs2_badNB_D_S}

flw_op

Floating-point loads and stores use the same base+offset addressing mode as the integer base ISAs, with a base address in register rs1 and a 12-bit signed byte offset. The FLW instruction loads a single-precision floating-point value from memory into floating-point register rd. FSW stores a single-precision value from floating-point register rs2 to memory.

D_flw_cg/{cp_NaNBox_D_S}

fmadd-s_op

FMADD.S multiplies the values in rs1 and rs2, adds the value in rs3, and writes the final result to rd. FMADD.S computes (rs1×rs2)+rs3. Floating-point fused multiply-add instructions require a new standard instruction format. R4-type instructions specify three source registers (rs1, rs2, and rs3) and a destination register (rd). This format is only used by the floating-point fused multiply-add instructions. The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. The fused multiply-add instructions must set the invalid operation exception flag when the multiplicands are ∞ and zero, even when the addend is a quiet NaN. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

D_fmadd_s_cg/{cp_NaNBox_D_S, cp_fs1_badNB_D_S, cp_fs2_badNB_D_S, cp_fs3_badNB_D_S}

fmax-s_op

Floating-point minimum-number and maximum-number instructions FMIN.S and FMAX.S write, respectively, the smaller or larger of rs1 and rs2 to rd

D_fmax_s_cg/{cp_NaNBox_D_S, cp_fs1_badNB_D_S, cp_fs2_badNB_D_S}

fmin-s_op

Floating-point minimum-number and maximum-number instructions FMIN.S and FMAX.S write, respectively, the smaller or larger of rs1 and rs2 to rd

D_fmin_s_cg/{cp_NaNBox_D_S, cp_fs1_badNB_D_S, cp_fs2_badNB_D_S}

fmsub-s_op

FMSUB.S multiplies the values in rs1 and rs2, subtracts the value in rs3, and writes the final result to rd. FMSUB.S computes (rs1×rs2)−rs3. Floating-point fused multiply-add instructions require a new standard instruction format. R4-type instructions specify three source registers (rs1, rs2, and rs3) and a destination register (rd). This format is only used by the floating-point fused multiply-add instructions. The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. The fused multiply-add instructions must set the invalid operation exception flag when the multiplicands are ∞ and zero, even when the addend is a quiet NaN. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

D_fmsub_s_cg/{cp_NaNBox_D_S, cp_fs1_badNB_D_S, cp_fs2_badNB_D_S, cp_fs3_badNB_D_S}

fmul-s_op

FADD.S and FMUL.S perform single-precision floating-point addition and multiplication respectively, between rs1 and rs2 In each case, the result is written to rd. The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

D_fmul_s_cg/{cp_NaNBox_D_S, cp_fs1_badNB_D_S, cp_fs2_badNB_D_S}

fmv-w-x_op

FMV.W.X moves the single-precision value encoded in IEEE 754-2008 standard encoding from the lower 32 bits of integer register rs1 to the floating-point register rd. The bits are not modified in the transfer, and in particular, the payloads of non-canonical NaNs are preserved.

D_fmv_w_x_cg/{cp_NaNBox_D_S}

fmv-x-w_op

FMV.X.W moves the single-precision value in floating-point register rs1 represented in IEEE 754-2008 encoding to the lower 32 bits of integer register rd. The bits are not modified in the transfer, and in particular, the payloads of non-canonical NaNs are preserved. For RV64, the higher 32 bits of the destination register are filled with copies of the floating-point number’s sign bit

D_fmv_x_w_cg/{cp_fs1_badNB_D_S}

fnmadd-s_op

FNMADD.S multiplies the values in rs1 and rs2, negates the product, subtracts the value in rs3, and writes the final result to rd. FNMADD.S computes −(rs1×rs2)−rs3. Floating-point fused multiply-add instructions require a new standard instruction format. R4-type instructions specify three source registers (rs1, rs2, and rs3) and a destination register (rd). This format is only used by the floating-point fused multiply-add instructions. The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. The fused multiply-add instructions must set the invalid operation exception flag when the multiplicands are ∞ and zero, even when the addend is a quiet NaN. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

D_fnmadd_s_cg/{cp_NaNBox_D_S, cp_fs1_badNB_D_S, cp_fs2_badNB_D_S, cp_fs3_badNB_D_S}

fnmsub-s_op

FNMSUB.S multiplies the values in rs1 and rs2, negates the product, adds the value in rs3, and writes the final result to rd. FNMSUB.S computes −(rs1×rs2)+rs3. Floating-point fused multiply-add instructions require a new standard instruction format. R4-type instructions specify three source registers (rs1, rs2, and rs3) and a destination register (rd). This format is only used by the floating-point fused multiply-add instructions. The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. The fused multiply-add instructions must set the invalid operation exception flag when the multiplicands are ∞ and zero, even when the addend is a quiet NaN. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

D_fnmsub_s_cg/{cp_NaNBox_D_S, cp_fs1_badNB_D_S, cp_fs2_badNB_D_S, cp_fs3_badNB_D_S}

fsgnj-s_op

Floating-point to floating-point sign-injection instructions, FSGNJ.S, FSGNJN.S, and FSGNJX.S, produce a result that takes all bits except the sign bit from rs1. For FSGNJ, the result’s sign bit is rs2’s sign bit; for FSGNJN, the result’s sign bit is the opposite of rs2’s sign bit; and for FSGNJX, the sign bit is the XOR of the sign bits of rs1 and rs2. Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension.

D_fsgnj_s_cg/{cp_NaNBox_D_S, cp_fs1_badNB_D_S, cp_fs2_badNB_D_S}

fsgnjn-s_op

Floating-point to floating-point sign-injection instructions, FSGNJ.S, FSGNJN.S, and FSGNJX.S, produce a result that takes all bits except the sign bit from rs1. For FSGNJ, the result’s sign bit is rs2’s sign bit; for FSGNJN, the result’s sign bit is the opposite of rs2’s sign bit; and for FSGNJX, the sign bit is the XOR of the sign bits of rs1 and rs2. Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension.

D_fsgnjn_s_cg/{cp_NaNBox_D_S, cp_fs1_badNB_D_S, cp_fs2_badNB_D_S}

fsgnjx-s_op

Floating-point to floating-point sign-injection instructions, FSGNJ.S, FSGNJN.S, and FSGNJX.S, produce a result that takes all bits except the sign bit from rs1. For FSGNJ, the result’s sign bit is rs2’s sign bit; for FSGNJN, the result’s sign bit is the opposite of rs2’s sign bit; and for FSGNJX, the sign bit is the XOR of the sign bits of rs1 and rs2. Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension.

D_fsgnjx_s_cg/{cp_NaNBox_D_S, cp_fs1_badNB_D_S, cp_fs2_badNB_D_S}

fsqrt-s_op

FSQRT.S computes the square root of rs1 In each case, the result is written to rd. The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

D_fsqrt_s_cg/{cp_NaNBox_D_S, cp_fs1_badNB_D_S}

fsub-s_op

FSUB.S performs the single-precision floating-point subtraction of rs2 from rs1 In each case, the result is written to rd. The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

D_fsub_s_cg/{cp_NaNBox_D_S, cp_fs1_badNB_D_S, cp_fs2_badNB_D_S}

fsw_op

Floating-point loads and stores use the same base+offset addressing mode as the integer base ISAs, with a base address in register rs1 and a 12-bit signed byte offset. The FLW instruction loads a single-precision floating-point value from memory into floating-point register rd. FSW stores a single-precision value from floating-point register rs2 to memory.

D_fsw_cg/{cp_fs2_badNB_D_S}

UDB Parameters: None.

A.7.3. Zfh Half-Precision FP

Table 47. Zfh Instruction Coverpoints
Instruction fadd.h fclass.h fcvt.h.l fcvt.h.lu fcvt.h.s fcvt.h.w fcvt.h.wu fcvt.l.h fcvt.lu.h

Type

FR

FIX

X2F

X2F

FI

X2F

X2F

F2X

F2X

RV32

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_rs1

x

x

x

x

cp_rd

x

x

x

cp_rs1_edges

x

x

x

x

cp_fs1

x

x

x

x

x

cp_fs2

x

cp_fd

x

x

x

x

x

x

cp_fs1_edges

H

H

frm

frm_H

frm_H

cp_fs2_edges

H

cmp_fd_fs1

x

x

cmp_fd_fs2

x

cp_frm

3

2

2

2

2

2

2

2

cp_csr_fflags

von

on

on

voun

on

on

vn

vn

cp_csr_frm

x

x

x

x

x

x

x

x

cr_fs1_fs2_edges

frm_H

cp_fclass

x

cp_NaNBox

S_H

S_H

S_H

S_H

S_H

S_H

cp_fs1_badNB

S_H

S_H

S_H

S_H

cp_fs2_badNB

S_H
Instruction fcvt.s.h fcvt.w.h fcvt.wu.h fdiv.h feq.h fle.h flh flt.h fmadd.h

Type

FI

F2X

F2X

FR

FC

FC

FL

FC

FR4

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_rs1

nx0

cp_rd

x

x

x

x

x

cp_imm_edges

x

cp_fs1

x

x

x

x

x

x

x

x

cp_fs2

x

x

x

x

x

cp_fs3

x

cp_fd

x

x

x

x

cp_fs1_edges

H

frm_H

frm_H

H

H

H

H

H

cp_fs2_edges

H

H

H

H

H

cp_fs3_edges

H

cmp_fd_fs1

x

x

x

cmp_fd_fs2

x

x

cmp_fd_fs3

x

cp_frm

2

2

3

4

cp_csr_fflags

v

vn

vn

vdoun

v

v

v

voun

cp_csr_frm

x

x

x

x

cr_fs1_fs2_edges

frm_H

H

H

H

frm4_H

cr_fs1_fs3_edges

frm4_H

cp_NaNBox

S_H

S_H

S_H

cp_fs1_badNB

S_H

S_H

S_H

S_H

S_H

S_H

S_H

S_H

cp_fs2_badNB

S_H

S_H

S_H

S_H

S_H

cp_fs3_badNB

S_H
Instruction fmax.h fmin.h fmsub.h fmul.h fmv.h.x fmv.x.h fnmadd.h fnmsub.h fsgnj.h

Type

FR

FR

FR4

FR

X2F

F2X

FR4

FR4

FR

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_rs1

x

cp_rd

x

cp_rs1_edges

x

cp_fs1

x

x

x

x

x

x

x

x

cp_fs2

x

x

x

x

x

x

x

cp_fs3

x

x

x

cp_fd

x

x

x

x

x

x

x

x

cp_fs1_edges

H

H

H

H

H

H

H

H

cp_fs2_edges

H

H

H

H

H

H

H

cp_fs3_edges

H

H

H

cmp_fd_fs1

x

x

x

x

x

x

x

cmp_fd_fs2

x

x

x

x

x

x

x

cmp_fd_fs3

x

x

x

cp_frm

4

3

4

4

cp_csr_fflags

v

v

voun

voun

voun

voun

cp_csr_frm

x

x

x

x

cr_fs1_fs2_edges

H

H

frm4_H

frm_H

frm4_H

frm4_H

H

cr_fs1_fs3_edges

frm4_H

frm4_H

frm4_H

cp_NaNBox

S_H

S_H

S_H

S_H

S_H

S_H

S_H

S_H

cp_fs1_badNB

S_H

S_H

S_H

S_H

S_H

S_H

S_H

S_H

cp_fs2_badNB

S_H

S_H

S_H

S_H

S_H

S_H

S_H

cp_fs3_badNB

S_H

S_H

S_H
Instruction fsgnjn.h fsgnjx.h fsh fsqrt.h fsub.h

Type

FR

FR

FS

FI

FR

RV32

x

x

x

x

x

RV64

x

x

x

x

x

cp_asm_count

x

x

x

x

x

cp_rs1

nx0

cp_imm_edges

x

cp_fs1

x

x

x

x

cp_fs2

x

x

x

x

cp_fd

x

x

x

x

cp_fs1_edges

H

H

H

H

cp_fs2_edges

H

H

H

H

cmp_fd_fs1

x

x

x

x

cmp_fd_fs2

x

x

x

cp_frm

2

3

cp_csr_fflags

vn

von

cp_csr_frm

x

x

cr_fs1_fs2_edges

H

H

frm_H

cp_NaNBox

S_H

S_H

S_H

S_H

cp_fs1_badNB

S_H

S_H

S_H

S_H

cp_fs2_badNB

S_H

S_H

S_H

S_H
Table 48. Zfh Normative Rules
Normative Rule Rule Text Coverpoints

fadd-h_op

FADD.S and FMUL.S perform single-precision floating-point addition and multiplication respectively, between rs1 and rs2 The half-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on half-precision operands and produce half-precision results. Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

Zfh_fadd_h_cg/{cp_fs1, cp_fs2, cp_fd, cp_frm_3, cp_csr_fflags_von, cp_csr_frm, cr_fs1_fs2_edges_frm_H, cp_NaNBox_S_H, cp_fs1_badNB_S_H, cp_fs2_badNB_S_H}

fclass-h_op

The FCLASS.S instruction examines the value in floating-point register rs1 and writes to integer register rd a 10-bit mask that indicates the class of the floating-point number. The format of the mask is described in . The corresponding bit in rd will be set if the property is true and clear otherwise. All other bits in rd are cleared. Note that exactly one bit in rd will be set. FCLASS.S does not set the floating-point exception flags. The half-precision floating-point classify instruction, FCLASS.H, is defined analogously to its single-precision counterpart, but operates on half-precision operands.

Zfh_fclass_h_cg/{cp_rd, cp_fs1, cp_fs1_edges_H, cp_fclass, cp_fs1_badNB_S_H}

fcvt-h-l_op

FCVT.H.W or FCVT.H.L converts a 32-bit or 64-bit signed integer, respectively, into a half-precision floating-point number All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. FCVT.L[U].H and FCVT.H.L[U] are RV64-only instructions. All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

Zfh_fcvt_h_l_cg/{cp_rs1, cp_rs1_edges, cp_fd, cp_frm_2, cp_csr_fflags_on, cp_csr_frm, cp_NaNBox_S_H}

fcvt-h-lu_op

FCVT.WU.H, FCVT.LU.H, FCVT.H.WU, and FCVT.H.LU variants convert to or from unsigned integer values All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. FCVT.L[U].H and FCVT.H.L[U] are RV64-only instructions. All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

Zfh_fcvt_h_lu_cg/{cp_rs1, cp_rs1_edges, cp_fd, cp_frm_2, cp_csr_fflags_on, cp_csr_frm, cp_NaNBox_S_H}

fcvt-h-s_op

FCVT.S.H or FCVT.H.S converts a half-precision floating-point number to a single-precision floating-point number, or vice-versa, respectively FCVT.S.D rounds according to the RM field; FCVT.D.S will never round

Zfh_fcvt_h_s_cg/{cp_fs1, cp_fd, cp_fs1_edges_frm, cp_frm_2, cp_csr_fflags_voun, cp_csr_frm, cp_NaNBox_S_H}

fcvt-h-w_op

FCVT.H.W or FCVT.H.L converts a 32-bit or 64-bit signed integer, respectively, into a half-precision floating-point number All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

Zfh_fcvt_h_w_cg/{cp_rs1, cp_rs1_edges, cp_fd, cp_frm_2, cp_csr_fflags_on, cp_csr_frm, cp_NaNBox_S_H}

fcvt-h-wu_op

FCVT.WU.H, FCVT.LU.H, FCVT.H.WU, and FCVT.H.LU variants convert to or from unsigned integer values All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

Zfh_fcvt_h_wu_cg/{cp_rs1, cp_rs1_edges, cp_fd, cp_frm_2, cp_csr_fflags_on, cp_csr_frm, cp_NaNBox_S_H}

fcvt-l-h_op

FCVT.W.H or FCVT.L.H converts a half-precision floating-point number to a signed 32-bit or 64-bit integer, respectively All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. FCVT.L[U].H and FCVT.H.L[U] are RV64-only instructions. [int_conv] gives the range of valid inputs for FCVT.int.S and the behavior for invalid inputs All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

Zfh_fcvt_l_h_cg/{cp_rd, cp_fs1, cp_fs1_edges_frm_H, cp_frm_2, cp_csr_fflags_vn, cp_csr_frm, cp_fs1_badNB_S_H}

fcvt-lu-h_op

FCVT.WU.H, FCVT.LU.H, FCVT.H.WU, and FCVT.H.LU variants convert to or from unsigned integer values All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. FCVT.L[U].H and FCVT.H.L[U] are RV64-only instructions. [int_conv] gives the range of valid inputs for FCVT.int.S and the behavior for invalid inputs All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

Zfh_fcvt_lu_h_cg/{cp_rd, cp_fs1, cp_fs1_edges_frm_H, cp_frm_2, cp_csr_fflags_vn, cp_csr_frm, cp_fs1_badNB_S_H}

fcvt-s-h_op

FCVT.S.H or FCVT.H.S converts a half-precision floating-point number to a single-precision floating-point number, or vice-versa, respectively FCVT.S.D rounds according to the RM field; FCVT.D.S will never round

Zfh_fcvt_s_h_cg/{cp_fs1, cp_fd, cp_fs1_edges_H, cp_csr_fflags_v, cp_fs1_badNB_S_H}

fcvt-w-h_op

FCVT.W.H or FCVT.L.H converts a half-precision floating-point number to a signed 32-bit or 64-bit integer, respectively All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. [int_conv] gives the range of valid inputs for FCVT.int.S and the behavior for invalid inputs All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

Zfh_fcvt_w_h_cg/{cp_rd, cp_fs1, cp_fs1_edges_frm_H, cp_frm_2, cp_csr_fflags_vn, cp_csr_frm, cp_fs1_badNB_S_H}

fcvt-wu-h_op

FCVT.WU.H, FCVT.LU.H, FCVT.H.WU, and FCVT.H.LU variants convert to or from unsigned integer values All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. [int_conv] gives the range of valid inputs for FCVT.int.S and the behavior for invalid inputs All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

Zfh_fcvt_wu_h_cg/{cp_rd, cp_fs1, cp_fs1_edges_frm_H, cp_frm_2, cp_csr_fflags_vn, cp_csr_frm, cp_fs1_badNB_S_H}

fdiv-h_op

FDIV.S performs the single-precision floating-point division of rs1 by rs2 The half-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on half-precision operands and produce half-precision results. Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

Zfh_fdiv_h_cg/{cp_fs1, cp_fs2, cp_fd, cp_frm_3, cp_csr_fflags_vdoun, cp_csr_frm, cr_fs1_fs2_edges_frm_H, cp_NaNBox_S_H, cp_fs1_badNB_S_H, cp_fs2_badNB_S_H}

feq-h_op

Floating-point compare instructions (FEQ.S, FLT.S, FLE.S) perform the specified comparison between floating-point registers (rs1 = rs2, rs1 < rs2, rs1 ≤ rs2) writing 1 to the integer register rd if the condition holds, and 0 otherwise. The half-precision floating-point compare instructions are defined analogously to their single-precision counterparts, but operate on half-precision operands.

Zfh_feq_h_cg/{cp_rd, cp_fs1, cp_fs2, cp_csr_fflags_v, cr_fs1_fs2_edges_H, cp_fs1_badNB_S_H, cp_fs2_badNB_S_H}

fle-h_op

Floating-point compare instructions (FEQ.S, FLT.S, FLE.S) perform the specified comparison between floating-point registers (rs1 = rs2, rs1 < rs2, rs1 ≤ rs2) writing 1 to the integer register rd if the condition holds, and 0 otherwise. The half-precision floating-point compare instructions are defined analogously to their single-precision counterparts, but operate on half-precision operands.

Zfh_fle_h_cg/{cp_rd, cp_fs1, cp_fs2, cp_csr_fflags_v, cr_fs1_fs2_edges_H, cp_fs1_badNB_S_H, cp_fs2_badNB_S_H}

flh_op

New 16-bit variants of LOAD-FP and STORE-FP instructions are added, encoded with a new value for the funct3 width field.

Zfh_flh_cg/{cp_rs1_nx0, cp_imm_edges, cp_fd, cp_NaNBox_S_H}

flt-h_op

Floating-point compare instructions (FEQ.S, FLT.S, FLE.S) perform the specified comparison between floating-point registers (rs1 = rs2, rs1 < rs2, rs1 ≤ rs2) writing 1 to the integer register rd if the condition holds, and 0 otherwise. The half-precision floating-point compare instructions are defined analogously to their single-precision counterparts, but operate on half-precision operands.

Zfh_flt_h_cg/{cp_rd, cp_fs1, cp_fs2, cp_csr_fflags_v, cr_fs1_fs2_edges_H, cp_fs1_badNB_S_H, cp_fs2_badNB_S_H}

fmadd-h_op

FMADD.S multiplies the values in rs1 and rs2, adds the value in rs3, and writes the final result to rd. FMADD.S computes (rs1×rs2)+rs3. The half-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on half-precision operands and produce half-precision results. Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. The fused multiply-add instructions must set the invalid operation exception flag when the multiplicands are ∞ and zero, even when the addend is a quiet NaN. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

Zfh_fmadd_h_cg/{cp_fs1, cp_fs2, cp_fs3, cp_fd, cp_frm_4, cp_csr_fflags_voun, cp_csr_frm, cr_fs1_fs2_edges_frm4_H, cr_fs1_fs3_edges_frm4_H, cp_NaNBox_S_H, cp_fs1_badNB_S_H, cp_fs2_badNB_S_H, cp_fs3_badNB_S_H}

fmsub-h_op

FMSUB.S multiplies the values in rs1 and rs2, subtracts the value in rs3, and writes the final result to rd. FMSUB.S computes (rs1×rs2)−rs3. The half-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on half-precision operands and produce half-precision results. Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. The fused multiply-add instructions must set the invalid operation exception flag when the multiplicands are ∞ and zero, even when the addend is a quiet NaN. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

Zfh_fmsub_h_cg/{cp_fs1, cp_fs2, cp_fs3, cp_fd, cp_frm_4, cp_csr_fflags_voun, cp_csr_frm, cr_fs1_fs2_edges_frm4_H, cr_fs1_fs3_edges_frm4_H, cp_NaNBox_S_H, cp_fs1_badNB_S_H, cp_fs2_badNB_S_H, cp_fs3_badNB_S_H}

fmul-h_op

FADD.S and FMUL.S perform single-precision floating-point addition and multiplication respectively, between rs1 and rs2 The half-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on half-precision operands and produce half-precision results. Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

Zfh_fmul_h_cg/{cp_fs1, cp_fs2, cp_fd, cp_frm_3, cp_csr_fflags_voun, cp_csr_frm, cr_fs1_fs2_edges_frm_H, cp_NaNBox_S_H, cp_fs1_badNB_S_H, cp_fs2_badNB_S_H}

fmv-h-x_op

FMV.D.X moves the double-precision value encoded in IEEE 754-2008 standard encoding from the integer register rs1 to the floating-point register rd FMV.H.X moves the half-precision value encoded in IEEE 754-2008 standard encoding from the lower 16 bits of integer register rs1 to the floating-point register rd, NaN-boxing the result.

Zfh_fmv_h_x_cg/{cp_rs1, cp_rs1_edges, cp_fd, cp_NaNBox_S_H}

fmv-x-h_op

FMV.X.D moves the double-precision value in floating-point register rs1 to a representation in IEEE 754-2008 standard encoding in integer register rd FMV.X.H moves the half-precision value in floating-point register rs1 to a representation in IEEE 754-2008 standard encoding in integer register rd, filling the upper XLEN-16 bits with copies of the floating-point number’s sign bit

Zfh_fmv_x_h_cg/{cp_rd, cp_fs1, cp_fs1_edges_H, cp_fs1_badNB_S_H}

fnmadd-h_op

FNMADD.S multiplies the values in rs1 and rs2, negates the product, subtracts the value in rs3, and writes the final result to rd. FNMADD.S computes −(rs1×rs2)−rs3. The half-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on half-precision operands and produce half-precision results. Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. The fused multiply-add instructions must set the invalid operation exception flag when the multiplicands are ∞ and zero, even when the addend is a quiet NaN. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

Zfh_fnmadd_h_cg/{cp_fs1, cp_fs2, cp_fs3, cp_fd, cp_frm_4, cp_csr_fflags_voun, cp_csr_frm, cr_fs1_fs2_edges_frm4_H, cr_fs1_fs3_edges_frm4_H, cp_NaNBox_S_H, cp_fs1_badNB_S_H, cp_fs2_badNB_S_H, cp_fs3_badNB_S_H}

fnmsub-h_op

FNMSUB.S multiplies the values in rs1 and rs2, negates the product, adds the value in rs3, and writes the final result to rd. FNMSUB.S computes −(rs1×rs2)+rs3. The half-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on half-precision operands and produce half-precision results. Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. The fused multiply-add instructions must set the invalid operation exception flag when the multiplicands are ∞ and zero, even when the addend is a quiet NaN. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

Zfh_fnmsub_h_cg/{cp_fs1, cp_fs2, cp_fs3, cp_fd, cp_frm_4, cp_csr_fflags_voun, cp_csr_frm, cr_fs1_fs2_edges_frm4_H, cr_fs1_fs3_edges_frm4_H, cp_NaNBox_S_H, cp_fs1_badNB_S_H, cp_fs2_badNB_S_H, cp_fs3_badNB_S_H}

fsgnj-h_op

Floating-point to floating-point sign-injection instructions, FSGNJ.H, FSGNJN.H, and FSGNJX.H are defined analogously to the single-precision sign-injection instruction. Floating-point to floating-point sign-injection instructions, FSGNJ.D, FSGNJN.D, and FSGNJX.D are defined analogously to the single-precision sign-injection instruction.

Zfh_fsgnj_h_cg/{cp_fs1, cp_fs2, cp_fd, cr_fs1_fs2_edges_H, cp_NaNBox_S_H, cp_fs1_badNB_S_H, cp_fs2_badNB_S_H}

fsgnjn-h_op

Floating-point to floating-point sign-injection instructions, FSGNJ.H, FSGNJN.H, and FSGNJX.H are defined analogously to the single-precision sign-injection instruction. Floating-point to floating-point sign-injection instructions, FSGNJ.D, FSGNJN.D, and FSGNJX.D are defined analogously to the single-precision sign-injection instruction.

Zfh_fsgnjn_h_cg/{cp_fs1, cp_fs2, cp_fd, cr_fs1_fs2_edges_H, cp_NaNBox_S_H, cp_fs1_badNB_S_H, cp_fs2_badNB_S_H}

fsgnjx-h_op

Floating-point to floating-point sign-injection instructions, FSGNJ.H, FSGNJN.H, and FSGNJX.H are defined analogously to the single-precision sign-injection instruction. Floating-point to floating-point sign-injection instructions, FSGNJ.D, FSGNJN.D, and FSGNJX.D are defined analogously to the single-precision sign-injection instruction.

Zfh_fsgnjx_h_cg/{cp_fs1, cp_fs2, cp_fd, cr_fs1_fs2_edges_H, cp_NaNBox_S_H, cp_fs1_badNB_S_H, cp_fs2_badNB_S_H}

fsh_op

New 16-bit variants of LOAD-FP and STORE-FP instructions are added, encoded with a new value for the funct3 width field.

Zfh_fsh_cg/{cp_rs1_nx0, cp_imm_edges, cp_fs2, cp_fs2_edges_H, cp_fs2_badNB_S_H}

fsqrt-h_op

FSQRT.S computes the square root of rs1 The half-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on half-precision operands and produce half-precision results. Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

Zfh_fsqrt_h_cg/{cp_fs1, cp_fd, cp_fs1_edges_H, cp_frm_2, cp_csr_fflags_vn, cp_csr_frm, cp_NaNBox_S_H, cp_fs1_badNB_S_H}

fsub-h_op

FSUB.S performs the single-precision floating-point subtraction of rs2 from rs1 The half-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on half-precision operands and produce half-precision results. Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

Zfh_fsub_h_cg/{cp_fs1, cp_fs2, cp_fd, cp_frm_3, cp_csr_fflags_von, cp_csr_frm, cr_fs1_fs2_edges_frm_H, cp_NaNBox_S_H, cp_fs1_badNB_S_H, cp_fs2_badNB_S_H}

UDB Parameters: None.

A.7.3.1. ZfhD
Table 49. ZfhD Normative Rules
Normative Rule Rule Text Coverpoints

fcvt-d-h_op

If the D extension is present, FCVT.D.H or FCVT.H.D converts a half-precision floating-point number to a double-precision floating-point number, or vice-versa, respectively FCVT.S.D rounds according to the RM field; FCVT.D.S will never round

ZfhD_fcvt_d_h_cg/{cp_fs1, cp_fd, cp_fs1_edges_H, cp_csr_fflags_v, cp_fs1_badNB_D_H}

fcvt-h-d_op

If the D extension is present, FCVT.D.H or FCVT.H.D converts a half-precision floating-point number to a double-precision floating-point number, or vice-versa, respectively FCVT.S.D rounds according to the RM field; FCVT.D.S will never round

ZfhD_fcvt_h_d_cg/{cp_fs1, cp_fd, cp_fs1_edges_frm_D, cp_frm_2, cp_csr_fflags_voun, cp_csr_frm, cp_NaNBox_D_H}

fadd-h_op

FADD.S and FMUL.S perform single-precision floating-point addition and multiplication respectively, between rs1 and rs2 The half-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on half-precision operands and produce half-precision results. Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

ZfhD_fadd_h_cg/{cp_NaNBox_D_H, cp_fs1_badNB_D_H, cp_fs2_badNB_D_H}

fclass-h_op

The FCLASS.S instruction examines the value in floating-point register rs1 and writes to integer register rd a 10-bit mask that indicates the class of the floating-point number. The format of the mask is described in . The corresponding bit in rd will be set if the property is true and clear otherwise. All other bits in rd are cleared. Note that exactly one bit in rd will be set. FCLASS.S does not set the floating-point exception flags. The half-precision floating-point classify instruction, FCLASS.H, is defined analogously to its single-precision counterpart, but operates on half-precision operands.

ZfhD_fclass_h_cg/{cp_fs1_badNB_D_H}

fcvt-h-l_op

FCVT.H.W or FCVT.H.L converts a 32-bit or 64-bit signed integer, respectively, into a half-precision floating-point number All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. FCVT.L[U].H and FCVT.H.L[U] are RV64-only instructions. All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

ZfhD_fcvt_h_l_cg/{cp_NaNBox_D_H}

fcvt-h-lu_op

FCVT.WU.H, FCVT.LU.H, FCVT.H.WU, and FCVT.H.LU variants convert to or from unsigned integer values All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. FCVT.L[U].H and FCVT.H.L[U] are RV64-only instructions. All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

ZfhD_fcvt_h_lu_cg/{cp_NaNBox_D_H}

fcvt-h-s_op

FCVT.S.H or FCVT.H.S converts a half-precision floating-point number to a single-precision floating-point number, or vice-versa, respectively FCVT.S.D rounds according to the RM field; FCVT.D.S will never round

ZfhD_fcvt_h_s_cg/{cp_NaNBox_D_H, cp_fs1_badNB_D_H}

fcvt-h-w_op

FCVT.H.W or FCVT.H.L converts a 32-bit or 64-bit signed integer, respectively, into a half-precision floating-point number All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

ZfhD_fcvt_h_w_cg/{cp_NaNBox_D_H}

fcvt-h-wu_op

FCVT.WU.H, FCVT.LU.H, FCVT.H.WU, and FCVT.H.LU variants convert to or from unsigned integer values All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

ZfhD_fcvt_h_wu_cg/{cp_NaNBox_D_H}

fcvt-l-h_op

FCVT.W.H or FCVT.L.H converts a half-precision floating-point number to a signed 32-bit or 64-bit integer, respectively All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. FCVT.L[U].H and FCVT.H.L[U] are RV64-only instructions. [int_conv] gives the range of valid inputs for FCVT.int.S and the behavior for invalid inputs All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

ZfhD_fcvt_l_h_cg/{cp_fs1_badNB_D_H}

fcvt-lu-h_op

FCVT.WU.H, FCVT.LU.H, FCVT.H.WU, and FCVT.H.LU variants convert to or from unsigned integer values All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. FCVT.L[U].H and FCVT.H.L[U] are RV64-only instructions. [int_conv] gives the range of valid inputs for FCVT.int.S and the behavior for invalid inputs All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

ZfhD_fcvt_lu_h_cg/{cp_fs1_badNB_D_H}

fcvt-s-h_op

FCVT.S.H or FCVT.H.S converts a half-precision floating-point number to a single-precision floating-point number, or vice-versa, respectively FCVT.S.D rounds according to the RM field; FCVT.D.S will never round

ZfhD_fcvt_s_h_cg/{cp_NaNBox_D_S, cp_fs1_badNB_D_H}

fcvt-w-h_op

FCVT.W.H or FCVT.L.H converts a half-precision floating-point number to a signed 32-bit or 64-bit integer, respectively All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. [int_conv] gives the range of valid inputs for FCVT.int.S and the behavior for invalid inputs All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

ZfhD_fcvt_w_h_cg/{cp_fs1_badNB_D_H}

fcvt-wu-h_op

FCVT.WU.H, FCVT.LU.H, FCVT.H.WU, and FCVT.H.LU variants convert to or from unsigned integer values All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W rd, x0, which will never set any exception flags. [int_conv] gives the range of valid inputs for FCVT.int.S and the behavior for invalid inputs All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

ZfhD_fcvt_wu_h_cg/{cp_fs1_badNB_D_H}

fdiv-h_op

FDIV.S performs the single-precision floating-point division of rs1 by rs2 The half-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on half-precision operands and produce half-precision results. Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

ZfhD_fdiv_h_cg/{cp_NaNBox_D_H, cp_fs1_badNB_D_H, cp_fs2_badNB_D_H}

feq-h_op

Floating-point compare instructions (FEQ.S, FLT.S, FLE.S) perform the specified comparison between floating-point registers (rs1 = rs2, rs1 < rs2, rs1 ≤ rs2) writing 1 to the integer register rd if the condition holds, and 0 otherwise. The half-precision floating-point compare instructions are defined analogously to their single-precision counterparts, but operate on half-precision operands.

ZfhD_feq_h_cg/{cp_fs1_badNB_D_H, cp_fs2_badNB_D_H}

fle-h_op

Floating-point compare instructions (FEQ.S, FLT.S, FLE.S) perform the specified comparison between floating-point registers (rs1 = rs2, rs1 < rs2, rs1 ≤ rs2) writing 1 to the integer register rd if the condition holds, and 0 otherwise. The half-precision floating-point compare instructions are defined analogously to their single-precision counterparts, but operate on half-precision operands.

ZfhD_fle_h_cg/{cp_fs1_badNB_D_H, cp_fs2_badNB_D_H}

flh_op

New 16-bit variants of LOAD-FP and STORE-FP instructions are added, encoded with a new value for the funct3 width field.

ZfhD_flh_cg/{cp_NaNBox_D_H}

flt-h_op

Floating-point compare instructions (FEQ.S, FLT.S, FLE.S) perform the specified comparison between floating-point registers (rs1 = rs2, rs1 < rs2, rs1 ≤ rs2) writing 1 to the integer register rd if the condition holds, and 0 otherwise. The half-precision floating-point compare instructions are defined analogously to their single-precision counterparts, but operate on half-precision operands.

ZfhD_flt_h_cg/{cp_fs1_badNB_D_H, cp_fs2_badNB_D_H}

fmadd-h_op

FMADD.S multiplies the values in rs1 and rs2, adds the value in rs3, and writes the final result to rd. FMADD.S computes (rs1×rs2)+rs3. The half-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on half-precision operands and produce half-precision results. Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. The fused multiply-add instructions must set the invalid operation exception flag when the multiplicands are ∞ and zero, even when the addend is a quiet NaN. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

ZfhD_fmadd_h_cg/{cp_NaNBox_D_H, cp_fs1_badNB_D_H, cp_fs2_badNB_D_H, cp_fs3_badNB_D_H}

fmsub-h_op

FMSUB.S multiplies the values in rs1 and rs2, subtracts the value in rs3, and writes the final result to rd. FMSUB.S computes (rs1×rs2)−rs3. The half-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on half-precision operands and produce half-precision results. Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. The fused multiply-add instructions must set the invalid operation exception flag when the multiplicands are ∞ and zero, even when the addend is a quiet NaN. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

ZfhD_fmsub_h_cg/{cp_NaNBox_D_H, cp_fs1_badNB_D_H, cp_fs2_badNB_D_H, cp_fs3_badNB_D_H}

fmul-h_op

FADD.S and FMUL.S perform single-precision floating-point addition and multiplication respectively, between rs1 and rs2 The half-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on half-precision operands and produce half-precision results. Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

ZfhD_fmul_h_cg/{cp_NaNBox_D_H, cp_fs1_badNB_D_H, cp_fs2_badNB_D_H}

fmv-h-x_op

FMV.D.X moves the double-precision value encoded in IEEE 754-2008 standard encoding from the integer register rs1 to the floating-point register rd FMV.H.X moves the half-precision value encoded in IEEE 754-2008 standard encoding from the lower 16 bits of integer register rs1 to the floating-point register rd, NaN-boxing the result.

ZfhD_fmv_h_x_cg/{cp_NaNBox_D_H}

fmv-x-h_op

FMV.X.D moves the double-precision value in floating-point register rs1 to a representation in IEEE 754-2008 standard encoding in integer register rd FMV.X.H moves the half-precision value in floating-point register rs1 to a representation in IEEE 754-2008 standard encoding in integer register rd, filling the upper XLEN-16 bits with copies of the floating-point number’s sign bit

ZfhD_fmv_x_h_cg/{cp_fs1_badNB_D_H}

fnmadd-h_op

FNMADD.S multiplies the values in rs1 and rs2, negates the product, subtracts the value in rs3, and writes the final result to rd. FNMADD.S computes −(rs1×rs2)−rs3. The half-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on half-precision operands and produce half-precision results. Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. The fused multiply-add instructions must set the invalid operation exception flag when the multiplicands are ∞ and zero, even when the addend is a quiet NaN. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

ZfhD_fnmadd_h_cg/{cp_NaNBox_D_H, cp_fs1_badNB_D_H, cp_fs2_badNB_D_H, cp_fs3_badNB_D_H}

fnmsub-h_op

FNMSUB.S multiplies the values in rs1 and rs2, negates the product, adds the value in rs3, and writes the final result to rd. FNMSUB.S computes −(rs1×rs2)+rs3. The half-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on half-precision operands and produce half-precision results. Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. The fused multiply-add instructions must set the invalid operation exception flag when the multiplicands are ∞ and zero, even when the addend is a quiet NaN. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

ZfhD_fnmsub_h_cg/{cp_NaNBox_D_H, cp_fs1_badNB_D_H, cp_fs2_badNB_D_H, cp_fs3_badNB_D_H}

fsgnj-h_op

Floating-point to floating-point sign-injection instructions, FSGNJ.H, FSGNJN.H, and FSGNJX.H are defined analogously to the single-precision sign-injection instruction. Floating-point to floating-point sign-injection instructions, FSGNJ.D, FSGNJN.D, and FSGNJX.D are defined analogously to the single-precision sign-injection instruction.

ZfhD_fsgnj_h_cg/{cp_NaNBox_D_H, cp_fs1_badNB_D_H, cp_fs2_badNB_D_H}

fsgnjn-h_op

Floating-point to floating-point sign-injection instructions, FSGNJ.H, FSGNJN.H, and FSGNJX.H are defined analogously to the single-precision sign-injection instruction. Floating-point to floating-point sign-injection instructions, FSGNJ.D, FSGNJN.D, and FSGNJX.D are defined analogously to the single-precision sign-injection instruction.

ZfhD_fsgnjn_h_cg/{cp_NaNBox_D_H, cp_fs1_badNB_D_H, cp_fs2_badNB_D_H}

fsgnjx-h_op

Floating-point to floating-point sign-injection instructions, FSGNJ.H, FSGNJN.H, and FSGNJX.H are defined analogously to the single-precision sign-injection instruction. Floating-point to floating-point sign-injection instructions, FSGNJ.D, FSGNJN.D, and FSGNJX.D are defined analogously to the single-precision sign-injection instruction.

ZfhD_fsgnjx_h_cg/{cp_NaNBox_D_H, cp_fs1_badNB_D_H, cp_fs2_badNB_D_H}

fsh_op

New 16-bit variants of LOAD-FP and STORE-FP instructions are added, encoded with a new value for the funct3 width field.

ZfhD_fsh_cg/{cp_fs2_badNB_D_H}

fsqrt-h_op

FSQRT.S computes the square root of rs1 The half-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on half-precision operands and produce half-precision results. Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

ZfhD_fsqrt_h_cg/{cp_NaNBox_D_H, cp_fs1_badNB_D_H}

fsub-h_op

FSUB.S performs the single-precision floating-point subtraction of rs2 from rs1 The half-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on half-precision operands and produce half-precision results. Apart from transfer operations described in the previous paragraph, all other floating-point operations on narrower n-bit operations, n<FLEN, check if the input operands are correctly NaN-boxed, i.e., all upper FLEN-n bits are 1. If so, the n least-significant bits of the input are used as the input value, otherwise the input value is treated as an n-bit canonical NaN. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

ZfhD_fsub_h_cg/{cp_NaNBox_D_H, cp_fs1_badNB_D_H, cp_fs2_badNB_D_H}

UDB Parameters: None.

A.7.3.2. Zfhmin
Table 50. Zfhmin Instruction Coverpoints
Instruction fcvt.h.s fcvt.s.h flh fmv.h.x fmv.x.h fsh

Type

FI

FI

FL

X2F

F2X

FS

RV32

x

x

x

x

x

x

RV64

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

cp_rs1

nx0

x

nx0

cp_rd

x

cp_rs1_edges

x

cp_imm_edges

x

x

cp_fs1

x

x

x

cp_fs2

x

cp_fd

x

x

x

x

cp_fs1_edges

x

H

H

cp_fs2_edges

H

cmp_fd_fs1

x

x

cp_frm

2

cp_csr_fflags

vn

v

cp_csr_frm

x

cp_NaNBox

S_H

S_H

S_H

cp_fs1_badNB

S_H

S_H

cp_fs2_badNB

S_H
Table 51. Zfhmin Normative Rules
Normative Rule Rule Text Coverpoints

fcvt-h-s_op

FCVT.S.H or FCVT.H.S converts a half-precision floating-point number to a single-precision floating-point number, or vice-versa, respectively FCVT.S.D rounds according to the RM field; FCVT.D.S will never round

Zfhmin_fcvt_h_s_cg/{cp_fs1, cp_fd, cp_fs1_edges, cp_frm_2, cp_csr_fflags_vn, cp_csr_frm, cp_NaNBox_S_H}

fcvt-s-h_op

FCVT.S.H or FCVT.H.S converts a half-precision floating-point number to a single-precision floating-point number, or vice-versa, respectively FCVT.S.D rounds according to the RM field; FCVT.D.S will never round

Zfhmin_fcvt_s_h_cg/{cp_fs1, cp_fd, cp_fs1_edges_H, cp_csr_fflags_v, cp_fs1_badNB_S_H}

flh_op

New 16-bit variants of LOAD-FP and STORE-FP instructions are added, encoded with a new value for the funct3 width field.

Zfhmin_flh_cg/{cp_rs1_nx0, cp_imm_edges, cp_fd, cp_NaNBox_S_H}

fmv-h-x_op

FMV.D.X moves the double-precision value encoded in IEEE 754-2008 standard encoding from the integer register rs1 to the floating-point register rd FMV.H.X moves the half-precision value encoded in IEEE 754-2008 standard encoding from the lower 16 bits of integer register rs1 to the floating-point register rd, NaN-boxing the result.

Zfhmin_fmv_h_x_cg/{cp_rs1, cp_rs1_edges, cp_fd, cp_NaNBox_S_H}

fmv-x-h_op

FMV.X.D moves the double-precision value in floating-point register rs1 to a representation in IEEE 754-2008 standard encoding in integer register rd FMV.X.H moves the half-precision value in floating-point register rs1 to a representation in IEEE 754-2008 standard encoding in integer register rd, filling the upper XLEN-16 bits with copies of the floating-point number’s sign bit

Zfhmin_fmv_x_h_cg/{cp_rd, cp_fs1, cp_fs1_edges_H, cp_fs1_badNB_S_H}

fsh_op

New 16-bit variants of LOAD-FP and STORE-FP instructions are added, encoded with a new value for the funct3 width field.

Zfhmin_fsh_cg/{cp_rs1_nx0, cp_imm_edges, cp_fs2, cp_fs2_edges_H, cp_fs2_badNB_S_H}

UDB Parameters: None.

A.7.3.3. ZfhminD
Table 52. ZfhminD Instruction Coverpoints
Instruction fcvt.h.s fcvt.s.h flh fmv.h.x fmv.x.h fsh

Type

FI

FI

FL

X2F

F2X

FS

RV32

x

x

x

x

x

x

RV64

x

x

x

x

x

x

cp_NaNBox

D_H

D_H

D_H

cp_fs1_badNB

D_H

D_H

cp_fs2_badNB

D_H
Table 53. ZfhminD Normative Rules
Normative Rule Rule Text Coverpoints

fcvt-h-s_op

FCVT.S.H or FCVT.H.S converts a half-precision floating-point number to a single-precision floating-point number, or vice-versa, respectively FCVT.S.D rounds according to the RM field; FCVT.D.S will never round

ZfhminD_fcvt_h_s_cg/{cp_NaNBox_D_H}

fcvt-s-h_op

FCVT.S.H or FCVT.H.S converts a half-precision floating-point number to a single-precision floating-point number, or vice-versa, respectively FCVT.S.D rounds according to the RM field; FCVT.D.S will never round

ZfhminD_fcvt_s_h_cg/{cp_fs1_badNB_D_H}

flh_op

New 16-bit variants of LOAD-FP and STORE-FP instructions are added, encoded with a new value for the funct3 width field.

ZfhminD_flh_cg/{cp_NaNBox_D_H}

fmv-h-x_op

FMV.D.X moves the double-precision value encoded in IEEE 754-2008 standard encoding from the integer register rs1 to the floating-point register rd FMV.H.X moves the half-precision value encoded in IEEE 754-2008 standard encoding from the lower 16 bits of integer register rs1 to the floating-point register rd, NaN-boxing the result.

ZfhminD_fmv_h_x_cg/{cp_NaNBox_D_H}

fmv-x-h_op

FMV.X.D moves the double-precision value in floating-point register rs1 to a representation in IEEE 754-2008 standard encoding in integer register rd FMV.X.H moves the half-precision value in floating-point register rs1 to a representation in IEEE 754-2008 standard encoding in integer register rd, filling the upper XLEN-16 bits with copies of the floating-point number’s sign bit

ZfhminD_fmv_x_h_cg/{cp_fs1_badNB_D_H}

fsh_op

New 16-bit variants of LOAD-FP and STORE-FP instructions are added, encoded with a new value for the funct3 width field.

ZfhminD_fsh_cg/{cp_fs2_badNB_D_H}

UDB Parameters: None.

A.7.4. Zfa Additional FP

Tests for Zfa for single-precision floating-point are called ZfaF.

Table 54. ZfaF Instruction Coverpoints
Instruction fleq.s fli.s fltq.s fmaxm.s fminm.s fround.s froundnx.s

Type

FC

FLI

FC

FR

FR

FI

FI

RV32

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

cp_rs1

fli

cp_rd

x

x

cp_fs1

x

x

x

x

x

x

cp_fs2

x

x

x

x

cp_fd

x

x

x

x

x

cp_fs1_edges

x

x

x

x

x

x

cp_fs2_edges

x

x

x

x

cmp_fd_fs1

x

x

x

x

cmp_fd_fs2

x

x

cp_frm

2

2

cp_csr_fflags

v

v

v

v

v

vn

cp_csr_frm

x

x

cr_fs1_fs2_edges

x

x

x

x
Table 55. ZfaF Normative Rules
Normative Rule Rule Text Coverpoints

fleq-s_op

The FLEQ.S and FLTQ.S instructions are defined like the FLE.S and FLT.S instructions, except that quiet NaN inputs do not cause the invalid operation exception flag to be set.

ZfaF_fleq_s_cg/{cp_rd, cp_fs1, cp_fs2, cp_csr_fflags_v, cr_fs1_fs2_edges}

fli-s_op

The FLI.S instruction loads one of 32 single-precision floating-point constants, encoded in the rs1 field, into floating-point register rd. The correspondence of rs1 field values and single-precision floating-point values is shown in . FLI.S is encoded like FMV.W.X, but with rs2=1.

ZfaF_fli_s_cg/{cp_rs1_fli, cp_fd}

fltq-s_op

The FLEQ.S and FLTQ.S instructions are defined like the FLE.S and FLT.S instructions, except that quiet NaN inputs do not cause the invalid operation exception flag to be set.

ZfaF_fltq_s_cg/{cp_rd, cp_fs1, cp_fs2, cp_csr_fflags_v, cr_fs1_fs2_edges}

fmaxm-s_op

The FMINM.S and FMAXM.S instructions are defined like the FMIN.S and FMAX.S instructions, except that if either input is NaN, the result is the canonical NaN.

ZfaF_fmaxm_s_cg/{cp_fs1, cp_fs2, cp_fd, cp_csr_fflags_v, cr_fs1_fs2_edges}

fminm-s_op

The FMINM.S and FMAXM.S instructions are defined like the FMIN.S and FMAX.S instructions, except that if either input is NaN, the result is the canonical NaN.

ZfaF_fminm_s_cg/{cp_fs1, cp_fs2, cp_fd, cp_csr_fflags_v, cr_fs1_fs2_edges}

fround-s_op

The FROUND.S instruction rounds the single-precision floating-point number in floating-point register rs1 to an integer, according to the rounding mode specified in the instruction’s rm field. It then writes that integer, represented as a single-precision floating-point number, to floating-point register rd

ZfaF_fround_s_cg/{cp_fs1, cp_fd, cp_fs1_edges, cp_frm_2, cp_csr_fflags_v, cp_csr_frm}

froundnx-s_op

The FROUNDNX.S instruction is defined similarly, but it also sets the inexact exception flag if the input differs from the rounded result and is not NaN. FROUNDNX.S is encoded like FCVT.S.D, but with rs2=5.

ZfaF_froundnx_s_cg/{cp_fs1, cp_fd, cp_fs1_edges, cp_frm_2, cp_csr_fflags_vn, cp_csr_frm}

UDB Parameters: None.

A.7.4.1. ZfaD
Table 56. ZfaD Instruction Coverpoints
Instruction fcvtmod.w.d fleq.d fli.d fltq.d fmaxm.d fminm.d fmvh.x.d fmvp.d.x fround.d

Type

F2X

FC

FLI

FC

FR

FR

F2X

PX2F

FI

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_rs1

fli

x

cp_rs2

x

cp_rd

x

x

x

x

cp_rs1_edges

x

cp_rs2_edges

x

cp_fs1

x

x

x

x

x

x

x

cp_fs2

x

x

x

x

cp_fd

x

x

x

x

x

cp_fs1_edges

D

D

D

D

D

D

D

cp_fs2_edges

D

D

D

D

cmp_fd_fs1

x

x

x

cmp_fd_fs2

x

x

cp_frm

2

cp_csr_fflags

vn

v

v

v

v

v

cp_csr_frm

x

cr_fs1_fs2_edges

D

D

D

D
Instruction froundnx.d

Type

FI

RV32

x

RV64

x

cp_asm_count

x

cp_fs1

x

cp_fd

x

cp_fs1_edges

D

cmp_fd_fs1

x

cp_frm

2

cp_csr_fflags

vn

cp_csr_frm

x
Instruction fleq.s fli.s fltq.s fmaxm.s fminm.s fround.s froundnx.s

Type

FC

FLI

FC

FR

FR

FI

FI

RV32

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

cp_NaNBox

D_S

D_S

D_S

D_S

D_S

cp_fs1_badNB

D_S

D_S

D_S

D_S

D_S

D_S

cp_fs2_badNB

D_S

D_S

D_S

D_S
Table 57. ZfaD Normative Rules
Normative Rule Rule Text Coverpoints

fcvtmod-w-d_op

The FCVTMOD.W.D instruction is defined similarly to the FCVT.W.D instruction, with the following differences. FCVTMOD.W.D always rounds towards zero. Bits 31:0 are taken from the rounded, unbounded two’s complement result, then sign-extended to XLEN bits and written to integer register rd. ±∞ and NaN are converted to zero.

ZfaD_fcvtmod_w_d_cg/{cp_rd, cp_fs1, cp_fs1_edges_D, cp_csr_fflags_vn}

fleq-d_op

If the D extension is implemented, FLEQ.D and FLTQ.D instructions are analogously defined to operate on double-precision numbers.

ZfaD_fleq_d_cg/{cp_rd, cp_fs1, cp_fs2, cp_csr_fflags_v, cr_fs1_fs2_edges_D}

fli-d_op

If the D extension is implemented, FLI.D performs the analogous operation, but loads a double-precision value into floating-point register rd. Note that entry 1 (corresponding to the minimum positive normal value) has a numerically different value for double-precision than for single-precision. FLI.D is encoded like FLI.S, but with fmt=D.

ZfaD_fli_d_cg/{cp_rs1_fli, cp_fd}

fltq-d_op

If the D extension is implemented, FLEQ.D and FLTQ.D instructions are analogously defined to operate on double-precision numbers.

ZfaD_fltq_d_cg/{cp_rd, cp_fs1, cp_fs2, cp_csr_fflags_v, cr_fs1_fs2_edges_D}

fmaxm-d_op

If the D extension is implemented, FMINM.D and FMAXM.D instructions are analogously defined to operate on double-precision numbers.

ZfaD_fmaxm_d_cg/{cp_fs1, cp_fs2, cp_fd, cp_csr_fflags_v, cr_fs1_fs2_edges_D}

fminm-d_op

If the D extension is implemented, FMINM.D and FMAXM.D instructions are analogously defined to operate on double-precision numbers.

ZfaD_fminm_d_cg/{cp_fs1, cp_fs2, cp_fd, cp_csr_fflags_v, cr_fs1_fs2_edges_D}

fmvh-x-d_op

For RV32 only, if the D extension is implemented, the FMVH.X.D instruction moves bits 63:32 of floating-point register rs1 into integer register rd. It is encoded in the OP-FP major opcode with funct3=0, rs2=1, and funct7=1110001.

ZfaD_fmvh_x_d_cg/{cp_rd, cp_fs1, cp_fs1_edges_D}

fmvp-d-x_op

For RV32 only, if the D extension is implemented, the FMVP.D.X instruction moves a double-precision number from a pair of integer registers into a floating-point register. Integer registers rs1 and rs2 supply bits 31:0 and 63:32, respectively; the result is written to floating-point register rd. FMVP.D.X is encoded in the OP-FP major opcode with funct3=0 and funct7=1011001.

ZfaD_fmvp_d_x_cg/{cp_rs1, cp_rs2, cp_rs1_edges, cp_rs2_edges, cp_fd}

fleq-s_op

The FLEQ.S and FLTQ.S instructions are defined like the FLE.S and FLT.S instructions, except that quiet NaN inputs do not cause the invalid operation exception flag to be set.

ZfaD_fleq_s_cg/{cp_fs1_badNB_D_S, cp_fs2_badNB_D_S}

fli-s_op

The FLI.S instruction loads one of 32 single-precision floating-point constants, encoded in the rs1 field, into floating-point register rd. The correspondence of rs1 field values and single-precision floating-point values is shown in . FLI.S is encoded like FMV.W.X, but with rs2=1.

ZfaD_fli_s_cg/{cp_NaNBox_D_S}

fltq-s_op

The FLEQ.S and FLTQ.S instructions are defined like the FLE.S and FLT.S instructions, except that quiet NaN inputs do not cause the invalid operation exception flag to be set.

ZfaD_fltq_s_cg/{cp_fs1_badNB_D_S, cp_fs2_badNB_D_S}

fmaxm-s_op

The FMINM.S and FMAXM.S instructions are defined like the FMIN.S and FMAX.S instructions, except that if either input is NaN, the result is the canonical NaN.

ZfaD_fmaxm_s_cg/{cp_NaNBox_D_S, cp_fs1_badNB_D_S, cp_fs2_badNB_D_S}

fminm-s_op

The FMINM.S and FMAXM.S instructions are defined like the FMIN.S and FMAX.S instructions, except that if either input is NaN, the result is the canonical NaN.

ZfaD_fminm_s_cg/{cp_NaNBox_D_S, cp_fs1_badNB_D_S, cp_fs2_badNB_D_S}

fround-s_op

The FROUND.S instruction rounds the single-precision floating-point number in floating-point register rs1 to an integer, according to the rounding mode specified in the instruction’s rm field. It then writes that integer, represented as a single-precision floating-point number, to floating-point register rd

ZfaD_fround_s_cg/{cp_NaNBox_D_S, cp_fs1_badNB_D_S}

froundnx-s_op

The FROUNDNX.S instruction is defined similarly, but it also sets the inexact exception flag if the input differs from the rounded result and is not NaN. FROUNDNX.S is encoded like FCVT.S.D, but with rs2=5.

ZfaD_froundnx_s_cg/{cp_NaNBox_D_S, cp_fs1_badNB_D_S}

UDB Parameters: None.

A.7.4.2. ZfaZfh
Table 58. ZfaZfh Instruction Coverpoints
Instruction fleq.h fli.h fltq.h fmaxm.h fminm.h fround.h froundnx.h

Type

FC

FLI

FC

FR

FR

FI

FI

RV32

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

cp_rs1

fli

cp_rd

x

x

cp_fs1

x

x

x

x

x

x

cp_fs2

x

x

x

x

cp_fd

x

x

x

x

x

cp_fs1_edges

H

H

H

H

H

H

cp_fs2_edges

H

H

H

H

cmp_fd_fs1

x

x

x

x

cmp_fd_fs2

x

x

cp_frm

2

2

cp_csr_fflags

v

v

v

v

v

vn

cp_csr_frm

x

x

cr_fs1_fs2_edges

H

H

H

H

cp_NaNBox

S_H

S_H

S_H

S_H

S_H

cp_fs1_badNB

S_H

S_H

S_H

S_H

S_H

S_H

cp_fs2_badNB

S_H

S_H

S_H

S_H
Table 59. ZfaZfh Normative Rules
Normative Rule Rule Text Coverpoints

fleq-h_op

If the Zfh extension is implemented, FLEQ.H and FLTQ.H instructions are analogously defined to operate on half-precision numbers.

ZfaZfh_fleq_h_cg/{cp_rd, cp_fs1, cp_fs2, cp_csr_fflags_v, cr_fs1_fs2_edges_H, cp_fs1_badNB_S_H, cp_fs2_badNB_S_H}

fli-h_op

If the Zfh or Zvfh extension is implemented, FLI.H performs the analogous operation, but loads a half-precision floating-point value into register rd. Note that entry 1 (corresponding to the minimum positive normal value) has a numerically different value for half-precision. Furthermore, since 216 is not representable in half-precision floating-point, entry 29 in the table instead loads positive infinity—i.e., it is redundant with entry 30. FLI.H is encoded like FLI.S, but with fmt=H.

ZfaZfh_fli_h_cg/{cp_rs1_fli, cp_fd, cp_NaNBox_S_H}

fltq-h_op

If the Zfh extension is implemented, FLEQ.H and FLTQ.H instructions are analogously defined to operate on half-precision numbers.

ZfaZfh_fltq_h_cg/{cp_rd, cp_fs1, cp_fs2, cp_csr_fflags_v, cr_fs1_fs2_edges_H, cp_fs1_badNB_S_H, cp_fs2_badNB_S_H}

fmaxm-h_op

If the Zfh extension is implemented, FMINM.H and FMAXM.H instructions are analogously defined to operate on half-precision numbers.

ZfaZfh_fmaxm_h_cg/{cp_fs1, cp_fs2, cp_fd, cp_csr_fflags_v, cr_fs1_fs2_edges_H, cp_NaNBox_S_H, cp_fs1_badNB_S_H, cp_fs2_badNB_S_H}

fminm-h_op

If the Zfh extension is implemented, FMINM.H and FMAXM.H instructions are analogously defined to operate on half-precision numbers.

ZfaZfh_fminm_h_cg/{cp_fs1, cp_fs2, cp_fd, cp_csr_fflags_v, cr_fs1_fs2_edges_H, cp_NaNBox_S_H, cp_fs1_badNB_S_H, cp_fs2_badNB_S_H}

UDB Parameters: None.

A.7.4.3. ZfaZfhD

When Zfa is supported with both Zfh and D, there are additional NAN-Boxing tests for 16-bit values in 64-bit registers.

Table 60. ZfaZfhD Instruction Coverpoints
Instruction fleq.h fli.h fltq.h fmaxm.h fminm.h fround.h froundnx.h

Type

FC

FLI

FC

FR

FR

FI

FI

RV32

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

cp_NaNBox

D_H

D_H

D_H

D_H

D_H

cp_fs1_badNB

D_H

D_H

D_H

D_H

S_H

D_H

cp_fs2_badNB

D_H

D_H

D_H

D_H
Table 61. ZfaZfhD Normative Rules
Normative Rule Rule Text Coverpoints

fleq-h_op

If the Zfh extension is implemented, FLEQ.H and FLTQ.H instructions are analogously defined to operate on half-precision numbers.

ZfaZfhD_fleq_h_cg/{cp_fs1_badNB_D_H, cp_fs2_badNB_D_H}

fli-h_op

If the Zfh or Zvfh extension is implemented, FLI.H performs the analogous operation, but loads a half-precision floating-point value into register rd. Note that entry 1 (corresponding to the minimum positive normal value) has a numerically different value for half-precision. Furthermore, since 216 is not representable in half-precision floating-point, entry 29 in the table instead loads positive infinity—i.e., it is redundant with entry 30. FLI.H is encoded like FLI.S, but with fmt=H.

ZfaZfhD_fli_h_cg/{cp_NaNBox_D_H}

fltq-h_op

If the Zfh extension is implemented, FLEQ.H and FLTQ.H instructions are analogously defined to operate on half-precision numbers.

ZfaZfhD_fltq_h_cg/{cp_fs1_badNB_D_H, cp_fs2_badNB_D_H}

fmaxm-h_op

If the Zfh extension is implemented, FMINM.H and FMAXM.H instructions are analogously defined to operate on half-precision numbers.

ZfaZfhD_fmaxm_h_cg/{cp_NaNBox_D_H, cp_fs1_badNB_D_H, cp_fs2_badNB_D_H}

fminm-h_op

If the Zfh extension is implemented, FMINM.H and FMAXM.H instructions are analogously defined to operate on half-precision numbers.

ZfaZfhD_fminm_h_cg/{cp_NaNBox_D_H, cp_fs1_badNB_D_H, cp_fs2_badNB_D_H}

UDB Parameters: None.

A.7.4.4. Zfbfmin Scalar BF16 Converts
Table 62. Zfbfmin Instruction Coverpoints
Instruction fcvt.bf16.s fcvt.s.bf16 flh fmv.h.x fmv.x.h fsh

Type

FI

FI

FL

X2F

F2X

FS

RV32

x

x

x

x

x

x

RV64

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

cp_rs1

nx0

x

nx0

cp_rd

x

cp_rs1_edges

x

cp_imm_edges

x

x

cp_fs1

x

x

x

cp_fs2

x

cp_fd

x

x

x

x

cp_fs1_edges

x

BF16

H

cp_fs2_edges

H

cmp_fd_fs1

x

x

cp_frm

2

cp_csr_fflags

vn

v

cp_csr_frm

x

cp_NaNBox

S_H

S_H

S_H

cp_fs1_badNB

S_H

S_H

cp_fs2_badNB

S_H
Table 63. Zfbfmin Normative Rules
Normative Rule Rule Text Coverpoints

fcvt-bf16-s_op

Narrowing convert FP32 value to a BF16 value. Round according to the RM field.

Zfbfmin_fcvt_bf16_s/{cp_fs1, cp_fd, cp_fs1_edges, cp_NaNBox_S_H}

fcvt-s-bf16_op

Converts a BF16 value to an FP32 value. The conversion is exact.

Zfbfmin_fcvt_bf16_s/{cp_fs1, cp_fd, cp_fs1_edges_H, cp_fs1_badNB_S_H}

UDB Parameters: None.

See also Zfhmin normative rules.

A.7.5. ZicsrF Floating-Point CSRs

These test additional CSRs that exist when floating-point is supported. Although these tests, like most privileged tests, are generated from a spreadsheet and manual coverpoints rather than a CSV, they do not assume any privileged capabilities, including the existence of machine mode. Hence they are compatible with RVI20 and simple cores that lack privileged modes.

Note that this suite also tests that the underflow flag is set only if the result is tiny after rounding, per the RISC-V spec.

Table 64. ZicsrF Coverpoints

Google Sheet Testplan
Table 65. ZicsrF Normative Rules
Normative Rule Rule Text Coverpoints

csrrc_op

The CSRRC (Atomic Read and Clear Bits in CSR) instruction reads the value of the CSR, zero-extends the value to XLEN bits, and writes it to integer register rd. The initial value in integer register rs1 is treated as a bit mask that specifies bit positions to be cleared in the CSR. Any bit that is high in rs1 will cause the corresponding bit to be cleared in the CSR, if that CSR bit is writable.

Zicsr_csrrc_cg/{cp_rs1, cp_rd, cp_rs1_edges}

csrrci_op

The CSRRWI, CSRRSI, and CSRRCI variants are similar to CSRRW, CSRRS, and CSRRC respectively, except they update the CSR using an XLEN-bit value obtained by zero-extending a 5-bit unsigned immediate (uimm[4:0]) field encoded in the rs1 field instead of a value from an integer register. For CSRRSI and CSRRCI, if the uimm[4:0] field is zero, then these instructions will not write to the CSR, and shall not cause any of the side effects that might otherwise occur on a CSR write, nor raise illegal-instruction exceptions on accesses to read-only CSRs. For CSRRWI, if rd=x0, then the instruction shall not read the CSR and shall not cause any of the side effects that might occur on a CSR read. Both CSRRSI and CSRRCI will always read the CSR and cause any read side effects regardless of rd and rs1 fields.

Zicsr_csrrci_cg/{cp_rd, cp_uimm_5}

csrrs_op

The CSRRS (Atomic Read and Set Bits in CSR) instruction reads the value of the CSR, zero-extends the value to XLEN bits, and writes it to integer register rd. The initial value in integer register rs1 is treated as a bit mask that specifies bit positions to be set in the CSR. Any bit that is high in rs1 will cause the corresponding bit to be set in the CSR, if that CSR bit is writable.

Zicsr_csrrs_cg/{cp_rs1, cp_rd, cp_rs1_edges}

csrrsi_op

The CSRRWI, CSRRSI, and CSRRCI variants are similar to CSRRW, CSRRS, and CSRRC respectively, except they update the CSR using an XLEN-bit value obtained by zero-extending a 5-bit unsigned immediate (uimm[4:0]) field encoded in the rs1 field instead of a value from an integer register. For CSRRSI and CSRRCI, if the uimm[4:0] field is zero, then these instructions will not write to the CSR, and shall not cause any of the side effects that might otherwise occur on a CSR write, nor raise illegal-instruction exceptions on accesses to read-only CSRs. For CSRRWI, if rd=x0, then the instruction shall not read the CSR and shall not cause any of the side effects that might occur on a CSR read. Both CSRRSI and CSRRCI will always read the CSR and cause any read side effects regardless of rd and rs1 fields.

Zicsr_csrrsi_cg/{cp_rd, cp_uimm_5}

csrrw_op

The CSRRW (Atomic Read/Write CSR) instruction atomically swaps values in the CSRs and integer registers. CSRRW reads the old value of the CSR, zero-extends the value to XLEN bits, then writes it to integer register rd. The initial value in rs1 is written to the CSR. If rd=x0, then the instruction shall not read the CSR and shall not cause any of the side effects that might occur on a CSR read.

Zicsr_csrrw_cg/{cp_rs1, cp_rd, cp_rs1_edges}

csrrwi_op

The CSRRWI, CSRRSI, and CSRRCI variants are similar to CSRRW, CSRRS, and CSRRC respectively, except they update the CSR using an XLEN-bit value obtained by zero-extending a 5-bit unsigned immediate (uimm[4:0]) field encoded in the rs1 field instead of a value from an integer register. For CSRRSI and CSRRCI, if the uimm[4:0] field is zero, then these instructions will not write to the CSR, and shall not cause any of the side effects that might otherwise occur on a CSR write, nor raise illegal-instruction exceptions on accesses to read-only CSRs. For CSRRWI, if rd=x0, then the instruction shall not read the CSR and shall not cause any of the side effects that might occur on a CSR read. Both CSRRSI and CSRRCI will always read the CSR and cause any read side effects regardless of rd and rs1 fields.

Zicsr_csrrwi_cg/{cp_rd, cp_uimm_5}

fscr_sz, fcsr_acc

The floating-point control and status register, fcsr, is a RISC-V control and status register (CSR). It is a 32-bit read/write register that selects the dynamic rounding mode for floating-point arithmetic operations and holds the accrued exception flags, as shown in .

ZicsrF_cg/{cp_fcsr_access, cp_fcsr_walk}

fcsr_op

The floating-point control and status register, fcsr, is a RISC-V control and status register (CSR). It is a 32-bit read/write register that selects the dynamic rounding mode for floating-point arithmetic operations and holds the accrued exception flags, as shown in . Bits 31—​8 of the fcsr are reserved for other standard extensions. If these extensions are not present, implementations shall ignore writes to these bits and supply a zero value when read. Standard software should preserve the contents of these bits.

ZicsrF_cg/cp_fflags_set, F_fadd_s_cg/cp_csr_frm

fcsr-frm_sz, fcsr-frm_acc

The fields within the fcsr can also be accessed individually through different CSR addresses, and separate assembler pseudoinstructions are defined for these accesses. The FRRM instruction reads the Rounding Mode field frm (fcsr bits 7—​5) and copies it into the least-significant three bits of integer register rd, with zero in all other bits. FSRM swaps the value in frm by copying the original value into integer register rd, and then writing a new value obtained from the three least-significant bits of integer register rs1 into frm. FRFLAGS and FSFLAGS are defined analogously for the Accrued Exception Flags field fflags (fcsr bits 4—​0).

ZicsrF_cg/{cp_fcsr_access, cp_fcsr_frm_write, cp_frm_write}

fcsr-frm_op

The fields within the fcsr can also be accessed individually through different CSR addresses, and separate assembler pseudoinstructions are defined for these accesses. The FRRM instruction reads the Rounding Mode field frm (fcsr bits 7—​5) and copies it into the least-significant three bits of integer register rd, with zero in all other bits. FSRM swaps the value in frm by copying the original value into integer register rd, and then writing a new value obtained from the three least-significant bits of integer register rs1 into frm. FRFLAGS and FSFLAGS are defined analogously for the Accrued Exception Flags field fflags (fcsr bits 4—​0). Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

F_fadd_s_cg/cp_csr_frm

fcsr-fflags_op

The fields within the fcsr can also be accessed individually through different CSR addresses, and separate assembler pseudoinstructions are defined for these accesses. The FRRM instruction reads the Rounding Mode field frm (fcsr bits 7—​5) and copies it into the least-significant three bits of integer register rd, with zero in all other bits. FSRM swaps the value in frm by copying the original value into integer register rd, and then writing a new value obtained from the three least-significant bits of integer register rs1 into frm. FRFLAGS and FSFLAGS are defined analogously for the Accrued Exception Flags field fflags (fcsr bits 4—​0). The accrued exception flags indicate the exception conditions that have arisen on any floating-point arithmetic instruction since the field was last reset by software, as shown in [bitdef]

ZicsrF_cg/{cp_fcsr_access, cp_fcsr_fflags_write, cp_fflags_write}

fmadd-s_op

FMADD.S multiplies the values in rs1 and rs2, adds the value in rs3, and writes the final result to rd. FMADD.S computes (rs1×rs2)+rs3. Floating-point fused multiply-add instructions require a new standard instruction format. R4-type instructions specify three source registers (rs1, rs2, and rs3) and a destination register (rd). This format is only used by the floating-point fused multiply-add instructions. The 2-bit floating-point format field fmt is encoded as shown in . It is set to S (00) for all instructions in the F extension. The fused multiply-add instructions must set the invalid operation exception flag when the multiplicands are ∞ and zero, even when the addend is a quiet NaN. Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard. In the parlance of the IEEE standard, tininess is detected after rounding. Rounding Mode|Mnemonic|Meaning === 000|RNE|Round to Nearest, ties to Even¶001|RTZ|Round towards Zero¶010|RDN|Round Down (towards −∞)¶011|RUP|Round Up (towards +∞)¶100|RMM|Round to Nearest, ties to Max Magnitude¶101||Reserved for future use.¶110||Reserved for future use.¶111|DYN|In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. === Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic rounding mode held in frm. Rounding modes are encoded as shown in [norm:dyn_round_enc]. A value of 111 in the instruction’s rm field selects the dynamic rounding mode held in frm

ZicsrF_cg/cp_underflow_after_rounding_*

UDB Parameters: None.

A.8. Zb* Bit Manipulation Extensions

A.8.1. Zba Bit-Manipulation for Addressing

Table 66. Zba Instruction Coverpoints
Instruction add.uw sh1add sh1add.uw sh2add sh2add.uw sh3add sh3add.uw slli.uw

Type

R

R

R

R

R

R

R

IS

RV32

x

x

x

RV64

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

cp_rs1

x

x

x

x

x

x

x

x

cp_rs2

x

x

x

x

x

x

x

cp_rd

x

x

x

x

x

x

x

x

cp_rs1_edges

x

x

x

x

x

x

x

x

cp_rs2_edges

x

x

x

x

x

x

x

cr_rs1_rs2_edges

x

x

x

x

x

x

x

cmp_rs1_rs2

x

x

x

x

x

x

x

cmp_rd_rs1

x

x

x

x

x

x

x

x

cmp_rd_rs2

x

x

x

x

x

x

x

cmp_rd_rs1_rs2

x

x

x

x

x

x

x

cp_uimm

x

A.8.2. Zbb Basic Bit-Manipulation

Table 67. Zbb Instruction Coverpoints
Instruction andn clz clzw cpop cpopw ctz ctzw max maxu

Type

R

I1

I1

I1

I1

I1

I1

R

R

RV32

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_rs1

x

x

x

x

x

x

x

x

x

cp_rs2

x

x

x

cp_rd

x

x

x

x

x

x

x

x

x

cp_rs1_edges

x

x

x

x

x

x

x

x

x

cp_rs2_edges

x

x

x

cr_rs1_rs2_edges

x

x

x

cmp_rs1_rs2

x

x

x

cmp_rd_rs1

x

x

x

x

x

x

x

x

x

cmp_rd_rs2

x

x

x

cmp_rd_rs1_rs2

x

x

x
Instruction min minu orc.b orn rev8 rol rolw ror rori

Type

R

R

I1

R

I1

R

R

R

IS

RV32

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_rs1

x

x

x

x

x

x

x

x

x

cp_rs2

x

x

x

x

x

x

cp_rd

x

x

x

x

x

x

x

x

x

cp_rs1_edges

x

x

orcb

x

x

x

x

x

x

cp_rs2_edges

x

x

x

x

x

x

cr_rs1_rs2_edges

x

x

x

x

x

x

cmp_rs1_rs2

x

x

x

x

x

x

cmp_rd_rs1

x

x

x

x

x

x

x

x

x

cmp_rd_rs2

x

x

x

x

x

x

cmp_rd_rs1_rs2

x

x

x

x

x

x

cp_uimm

x
Instruction roriw rorw sext.b sext.h xnor zext.h

Type

ISW

R

I1

I1

R

I1

RV32

x

x

x

x

RV64

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

cp_rs1

x

x

x

x

x

x

cp_rs2

x

x

cp_rd

x

x

x

x

x

x

cp_rs1_edges

x

x

x

x

x

x

cp_rs2_edges

x

x

cr_rs1_rs2_edges

x

x

cmp_rs1_rs2

x

x

cmp_rd_rs1

x

x

x

x

x

x

cmp_rd_rs2

x

x

cmp_rd_rs1_rs2

x

x

cp_uimm

5

A.8.3. Zbc Carry-less Multiplication

Table 68. Zbc Instruction Coverpoints
Instruction clmul clmulh clmulr

Type

R

R

R

RV32

x

x

x

RV64

x

x

x

cp_asm_count

x

x

x

cp_rs1

x

x

x

cp_rs2

x

x

x

cp_rd

x

x

x

cp_rs1_edges

x

x

x

cp_rs2_edges

x

x

x

cr_rs1_rs2_edges

x

x

x

cmp_rs1_rs2

x

x

x

cmp_rd_rs1

x

x

x

cmp_rd_rs2

x

x

x

cmp_rd_rs1_rs2

x

x

x

A.8.4. Zbs Single-Bit Manipulation

Table 69. Zbs Instruction Coverpoints
Instruction bclr bclri bext bexti binv binvi bset bseti

Type

R

IS

R

IS

R

IS

R

IS

RV32

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

cp_rs1

x

x

x

x

x

x

x

x

cp_rs2

x

x

x

x

cp_rd

x

x

x

x

x

x

x

x

cp_rs1_edges

x

x

x

x

x

x

x

x

cp_rs2_edges

x

x

x

x

cr_rs1_rs2_edges

x

x

x

x

cmp_rs1_rs2

x

x

x

x

cmp_rd_rs1

x

x

x

x

x

x

x

x

cmp_rd_rs2

x

x

x

x

cmp_rd_rs1_rs2

x

x

x

x

cp_uimm

x

x

x

x

A.8.5. Zbkb Bit-Manipulation for Cryptography

Table 70. Zbkb Instruction Coverpoints
Instruction andn brev8 orn pack packh rev8 rol ror rori

Type

R

I1

R

R

R

I1

R

R

IS

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_rs1

x

x

x

x

x

x

x

x

x

cp_rs2

x

x

nx0

x

x

x

cp_rd

x

x

x

x

x

x

x

x

x

cp_rs1_edges

x

x

x

x

x

x

x

x

x

cp_rs2_edges

x

x

x

x

x

x

cr_rs1_rs2_edges

x

x

x

x

x

x

cmp_rs1_rs2

x

x

nx0

x

x

x

cmp_rd_rs1

x

x

x

x

x

x

x

x

cmp_rd_rs2

x

x

nx0

x

x

x

cmp_rd_rs1_rs2

x

x

nx0

x

x

x

cp_uimm

x
Instruction unzip xnor zip

Type

I1

R

I1

RV32

x

x

x

RV64

x

cp_asm_count

x

x

x

cp_rs1

x

x

x

cp_rs2

x

cp_rd

x

x

x

cp_rs1_edges

x

x

x

cp_rs2_edges

x

cr_rs1_rs2_edges

x

cmp_rs1_rs2

x

cmp_rd_rs1

x

x

x

cmp_rd_rs2

x

cmp_rd_rs1_rs2

x

A.8.6. Zbkc Carry-less Multiplication for Cryptography

Table 71. Zbkc Instruction Coverpoints
Instruction clmul clmulh

Type

R

R

RV32

x

x

RV64

x

x

cp_asm_count

x

x

cp_rs1

x

x

cp_rs2

x

x

cp_rd

x

x

cp_rs1_edges

x

x

cp_rs2_edges

x

x

cr_rs1_rs2_edges

x

x

cmp_rs1_rs2

x

x

cmp_rd_rs1

x

x

cmp_rd_rs2

x

x

cmp_rd_rs1_rs2

x

x

A.8.7. Zbkx Permutation

Table 72. Zbkx Instruction Coverpoints
Instruction xperm4 xperm8

Type

R

R

RV32

x

x

RV64

x

x

cp_asm_count

x

x

cp_rs1

x

x

cp_rs2

x

x

cp_rd

x

x

cp_rs1_edges

x

x

cp_rs2_edges

x

x

cr_rs1_rs2_edges

x

x

cmp_rs1_rs2

x

x

cmp_rd_rs1

x

x

cmp_rd_rs2

x

x

cmp_rd_rs1_rs2

x

x

A.9. Zk* Cryptographic Extensions

A.9.1. Zkne NIST AES Encryption

Table 73. Zkne Instruction Coverpoints
Instruction aes32esi aes32esmi aes64es aes64esm aes64ks1i aes64ks2

Type

RB

RB

R

R

IR

R

RV32

x

x

RV64

x

x

x

x

cp_asm_count

x

x

x

x

x

x

cp_rs1

x

x

x

x

x

x

cp_rs2

x

x

x

x

x

cp_rd

x

x

x

x

x

x

cp_rs1_edges

x

x

x

x

x

x

cp_rs2_edges

x

x

x

x

x

cr_rs1_rs2_edges

x

x

x

x

x

cmp_rs1_rs2

x

x

x

x

x

cmp_rd_rs1

x

x

x

x

x

x

cmp_rd_rs2

x

x

x

x

x

cmp_rd_rs1_rs2

x

x

x

x

x

cp_bs

x

x

cp_rnum

x

cp_sbox

x

x

x

x

A.9.2. Zknd NIST AES Decryption

Table 74. Zknd Instruction Coverpoints
Instruction aes32dsi aes32dsmi aes64ds aes64dsm aes64im

Type

RB

RB

R

R

I1

RV32

x

x

RV64

x

x

x

cp_asm_count

x

x

x

x

x

cp_rs1

x

x

x

x

x

cp_rs2

x

x

x

x

cp_rd

x

x

x

x

x

cp_rs1_edges

x

x

x

x

x

cp_rs2_edges

x

x

x

x

cr_rs1_rs2_edges

x

x

x

x

cmp_rs1_rs2

x

x

x

x

cmp_rd_rs1

x

x

x

x

x

cmp_rd_rs2

x

x

x

x

cmp_rd_rs1_rs2

x

x

x

x

cp_bs

x

x

cp_sbox

x

x

x

x

A.9.3. Zknh NIST SHA2 Hashing

Table 75. Zknh Instruction Coverpoints
Instruction sha256sig0 sha256sig1 sha256sum0 sha256sum1 sha512sig0 sha512sig0h sha512sig0l sha512sig1 sha512sig1h

Type

I1

I1

I1

I1

I1

R

R

I1

R

RV32

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_rs1

x

x

x

x

x

x

x

x

x

cp_rs2

x

x

x

cp_rd

x

x

x

x

x

x

x

x

x

cp_rs1_edges

x

x

x

x

x

x

x

x

x

cp_rs2_edges

x

x

x

cr_rs1_rs2_edges

x

x

x

cmp_rs1_rs2

x

x

x

cmp_rd_rs1

x

x

x

x

x

x

x

x

x

cmp_rd_rs2

x

x

x

cmp_rd_rs1_rs2

x

x

x
Instruction sha512sig1l sha512sum0 sha512sum0r sha512sum1 sha512sum1r

Type

R

I1

R

I1

R

RV32

x

x

x

RV64

x

x

cp_asm_count

x

x

x

x

x

cp_rs1

x

x

x

x

x

cp_rs2

x

x

x

cp_rd

x

x

x

x

x

cp_rs1_edges

x

x

x

x

x

cp_rs2_edges

x

x

x

cr_rs1_rs2_edges

x

x

x

cmp_rs1_rs2

x

x

x

cmp_rd_rs1

x

x

x

x

x

cmp_rd_rs2

x

x

x

cmp_rd_rs1_rs2

x

x

x

A.9.4. Zksed ShangMi SM4 Block Cipher

Table 76. Zksed Instruction Coverpoints
Instruction sm4ed sm4ks

Type

RB

RB

RV32

x

x

RV64

x

x

cp_asm_count

x

x

cp_rs1

x

x

cp_rs2

x

x

cp_rd

x

x

cp_rs1_edges

x

x

cp_rs2_edges

x

x

cr_rs1_rs2_edges

x

x

cmp_rs1_rs2

x

x

cmp_rd_rs1

x

x

cmp_rd_rs2

x

x

cmp_rd_rs1_rs2

x

x

cp_bs

x

x

cp_sbox

x

x

A.9.5. Zksh ShangMi SM3 Hashing

Table 77. Zksh Instruction Coverpoints
Instruction sm3p0 sm3p1

Type

I1

I1

RV32

x

x

RV64

x

x

cp_asm_count

x

x

cp_rs1

x

x

cp_rd

x

x

cp_rs1_edges

x

x

cmp_rd_rs1

x

x

A.10. Zi* Additional Unpriv Extensions

This section includes a variety of unprivileged extensions.

A.10.1. Zicsr Control/Status Register Instructions

Table 78. Zicsr Instruction Coverpoints
Instruction csrrc csrrci csrrs csrrsi csrrw csrrwi

Type

CSR

CSRI

CSR

CSRI

CSR

CSRI

RV32

x

x

x

x

x

x

RV64

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

cp_rs1

x

x

x

cp_rd

x

x

x

x

x

x

cp_rs1_edges

x

x

x

cmp_rd_rs1

x

x

x

cp_uimm

5

5

5
Table 79. Zicsr Normative Rules
Normative Rule Rule Text Coverpoints

csrrc_op

The CSRRC (Atomic Read and Clear Bits in CSR) instruction reads the value of the CSR, zero-extends the value to XLEN bits, and writes it to integer register rd. The initial value in integer register rs1 is treated as a bit mask that specifies bit positions to be cleared in the CSR. Any bit that is high in rs1 will cause the corresponding bit to be cleared in the CSR, if that CSR bit is writable.

Zicsr_csrrc_cg/{cp_rs1, cp_rd, cp_rs1_edges}

csrrci_op

The CSRRWI, CSRRSI, and CSRRCI variants are similar to CSRRW, CSRRS, and CSRRC respectively, except they update the CSR using an XLEN-bit value obtained by zero-extending a 5-bit unsigned immediate (uimm[4:0]) field encoded in the rs1 field instead of a value from an integer register. For CSRRSI and CSRRCI, if the uimm[4:0] field is zero, then these instructions will not write to the CSR, and shall not cause any of the side effects that might otherwise occur on a CSR write, nor raise illegal-instruction exceptions on accesses to read-only CSRs. For CSRRWI, if rd=x0, then the instruction shall not read the CSR and shall not cause any of the side effects that might occur on a CSR read. Both CSRRSI and CSRRCI will always read the CSR and cause any read side effects regardless of rd and rs1 fields.

Zicsr_csrrci_cg/{cp_rd, cp_uimm_5}

csrrs_op

The CSRRS (Atomic Read and Set Bits in CSR) instruction reads the value of the CSR, zero-extends the value to XLEN bits, and writes it to integer register rd. The initial value in integer register rs1 is treated as a bit mask that specifies bit positions to be set in the CSR. Any bit that is high in rs1 will cause the corresponding bit to be set in the CSR, if that CSR bit is writable.

Zicsr_csrrs_cg/{cp_rs1, cp_rd, cp_rs1_edges}

csrrsi_op

The CSRRWI, CSRRSI, and CSRRCI variants are similar to CSRRW, CSRRS, and CSRRC respectively, except they update the CSR using an XLEN-bit value obtained by zero-extending a 5-bit unsigned immediate (uimm[4:0]) field encoded in the rs1 field instead of a value from an integer register. For CSRRSI and CSRRCI, if the uimm[4:0] field is zero, then these instructions will not write to the CSR, and shall not cause any of the side effects that might otherwise occur on a CSR write, nor raise illegal-instruction exceptions on accesses to read-only CSRs. For CSRRWI, if rd=x0, then the instruction shall not read the CSR and shall not cause any of the side effects that might occur on a CSR read. Both CSRRSI and CSRRCI will always read the CSR and cause any read side effects regardless of rd and rs1 fields.

Zicsr_csrrsi_cg/{cp_rd, cp_uimm_5}

csrrw_op

The CSRRW (Atomic Read/Write CSR) instruction atomically swaps values in the CSRs and integer registers. CSRRW reads the old value of the CSR, zero-extends the value to XLEN bits, then writes it to integer register rd. The initial value in rs1 is written to the CSR. If rd=x0, then the instruction shall not read the CSR and shall not cause any of the side effects that might occur on a CSR read.

Zicsr_csrrw_cg/{cp_rs1, cp_rd, cp_rs1_edges}

csrrwi_op

The CSRRWI, CSRRSI, and CSRRCI variants are similar to CSRRW, CSRRS, and CSRRC respectively, except they update the CSR using an XLEN-bit value obtained by zero-extending a 5-bit unsigned immediate (uimm[4:0]) field encoded in the rs1 field instead of a value from an integer register. For CSRRSI and CSRRCI, if the uimm[4:0] field is zero, then these instructions will not write to the CSR, and shall not cause any of the side effects that might otherwise occur on a CSR write, nor raise illegal-instruction exceptions on accesses to read-only CSRs. For CSRRWI, if rd=x0, then the instruction shall not read the CSR and shall not cause any of the side effects that might occur on a CSR read. Both CSRRSI and CSRRCI will always read the CSR and cause any read side effects regardless of rd and rs1 fields.

Zicsr_csrrwi_cg/{cp_rd, cp_uimm_5}

UDB Parameters: None.

=== TRAP_ON_UNIMPLEMENTED_CSR affects the results of Ssstrict/cp_csrr (SsstrictS Coverpoints). It does not affect Zicsr because this is an unprivileged test that should never perform operations that trap. ===

A.10.2. Zifencei Instruction-Fetch Fence

Table 80. Zifencei Instruction Coverpoints
Instruction fence.i

Type

I

RV32

x

RV64

x

cp_asm_count

x

cp_custom

fencei
Table 81. Zifencei Normative Rules
Normative Rule Rule Text Coverpoints

fence_i_op

A FENCE.I instruction orders all explicit memory accesses that precede the FENCE.I in program order before all instruction fetches that follow the FENCE.I in program order.

Zifencei_fence_i_cg/{cp_custom_fencei}

fence_i_rsv

The unused fields in the FENCE.I instruction, funct12, rs1, and rd, are reserved for finer-grain fences in future extensions. For forward compatibility, base implementations shall ignore these fields, and standard software shall zero these fields.

Zifencei_fence_i_cg/{cp_custom_fencei}

UDB Parameters: None.

Table 82. Zifencei Coverpoint Definitions
Coverpoint Bins Definition

cp_custom_fencei

4

Executes normal fence.i and fence.i instructions with nonzero rs1, rd, and funct12 fields to verify that they execute without trapping.

The Zifencei tests must write an instruction to an address, execute fence.i, and then execute the instruction to check that the new instruction is executed.

A.10.3. Misalign: Misaligned Loads/Stores

Misaligned loads/stores to main memory optionally can be handled in hardware. When the UDB MISALIGNED_LDST parameter is true, misaligned scalar loads and stores to main memory do not throw an exception. This parameter is a simplification of the "Access Type PMAs" which could define misaligned behavior on each memory region.

The misaligned family of tests exercises integer, compressed, and single/double/quad-precision floating-point loads/stores. It uses the new cp_misalign coverpoint defined in [t-Misaligned-modified-coverpoints]. It assumes that if these work, then Zfh and Zcb loads/stores will also work correctly. TODO: Add Vector misaligned. Misaligned atomics are exercised with {ExceptionsZaamo, ExceptionsZalrsc}/{cp_amo/load/store_address_misaligned}.

Table 83. Misalign Instruction Coverpoints
Instruction ld lh lhu lw lwu sd sh sw

Type

L

L

L

L

L

S

S

S

RV32

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

cp_misalign

x

x

x

x

x

x

x

x
Table 84. Misalign Normative Rules
Normative Rule Rule Text Coverpoints

MISALIGNED_LDST_FULLY_HW_SUPPORTED

misaligned loads and stores can be handled in hardware

{Misalign_lw_cg,Misalign_sw_cg}/{cp_misalign}

lh_op

LH loads a 16-bit value from memory, then sign-extends to 32-bits before storing in rd.

Misalign_lh_cg/{cp_misalign}

lhu_op

LHU loads a 16-bit value from memory but then zero extends to 32-bits before storing in rd.

Misalign_lhu_cg/{cp_misalign}

lw_op

The LW instruction loads a 32-bit value from memory into rd.

Misalign_lw_cg/{cp_misalign}

sh_op

The SW, SH, and SB instructions store 32-bit, 16-bit, and 8-bit values from the low bits of register rs2 to memory.

Misalign_sh_cg/{cp_misalign}

sw_op

The SW, SH, and SB instructions store 32-bit, 16-bit, and 8-bit values from the low bits of register rs2 to memory.

Misalign_sw_cg/{cp_misalign}

lwu_op

The LWU instruction, on the other hand, zero-extends the 32-bit value from memory for RV64I.

Misalign_lwu_cg/{cp_misalign}

ld_op_rv64i

The LD instruction loads a 64-bit value from memory into register rd for RV64I.

Misalign_ld_cg/{cp_misalign}

sd_op_rv64i

The SD, SW, SH, and SB instructions store 64-bit, 32-bit, 16-bit, and 8-bit values from the low bits of register rs2 to memory respectively.

Misalign_sd_cg/{cp_misalign}
Table 85. Misalign UDB Parameters
Parameter Description Coverpoint Effect

MISALIGNED_LDST

Does the implementation perform non-atomic misaligned loads and stores to main memory (does not affect misaligned support to device memory)? If not, the implementation always throws a misaligned exception.

cp_misalign

Coverpoints only run if True, and should not throw exceptions
Table 86. MisalignF Instruction Coverpoints
Instruction flw fsw

Type

FL

FS

RV32

x

x

RV64

x

x

cp_asm_count

x

x

cp_misalign

x

x
Table 87. MisalignF Normative Rules
Normative Rule Rule Text Coverpoints

MISALIGNED_LDST_FULLY_HW_SUPPORTED

misaligned loads and stores can be handled in hardware

{MisalignF_flw_cg,MisalignF_fsw_cg}/{cp_misalign}

fp_misaligned

As described in , the execution environment defines whether misaligned floating-point loads and stores are handled invisibly or raise a contained or fatal trap.

{MisalignF_flw_cg,MisalignF_fsw_cg}/{cp_misalign}

flw_op

Floating-point loads and stores use the same base+offset addressing mode as the integer base ISAs, with a base address in register rs1 and a 12-bit signed byte offset. The FLW instruction loads a single-precision floating-point value from memory into floating-point register rd. FSW stores a single-precision value from floating-point register rs2 to memory.

MisalignF_flw_cg/{cp_misalign}

fsw_op

Floating-point loads and stores use the same base+offset addressing mode as the integer base ISAs, with a base address in register rs1 and a 12-bit signed byte offset. The FLW instruction loads a single-precision floating-point value from memory into floating-point register rd. FSW stores a single-precision value from floating-point register rs2 to memory.

MisalignF_fsw_cg/{cp_misalign}

UDB Parameters: None.

Table 88. MisalignD Instruction Coverpoints
Instruction fld fsd

Type

FL

FS

RV32

x

x

RV64

x

x

cp_asm_count

x

x

cp_misalign

x

x
Table 89. MisalignD Normative Rules
Normative Rule Rule Text Coverpoints

MISALIGNED_LDST_FULLY_HW_SUPPORTED

misaligned loads and stores can be handled in hardware

{MisalignD_fld_cg,MisalignD_fsd_cg}/{cp_misalign}

fp_misaligned

As described in , the execution environment defines whether misaligned floating-point loads and stores are handled invisibly or raise a contained or fatal trap.

{MisalignD_fld_cg,MisalignD_fsd_cg}/{cp_misalign}

fld_op

The FLD instruction loads a double-precision floating-point value from memory into floating-point register rd

MisalignD_fld_cg/{cp_misalign}

fsd_op

FSD stores a double-precision value from the floating-point registers to memory

MisalignD_fsd_cg/{cp_misalign}

UDB Parameters: None.

Table 90. MisalignQ Normative Rules
Normative Rule Rule Text Coverpoints

MISALIGNED_LDST_FULLY_HW_SUPPORTED

misaligned loads and stores can be handled in hardware

{MisalignQ_flq_cg,MisalignQ_fsq_cg}/{cp_misalign}

fp_misaligned

As described in , the execution environment defines whether misaligned floating-point loads and stores are handled invisibly or raise a contained or fatal trap.

{MisalignQ_flq_cg,MisalignQ_fsq_cg}/{cp_misalign}

flq_op

New 128-bit variants of LOAD-FP and STORE-FP instructions are added, encoded with a new value for the funct3 width field.

MisalignQ_flq_cg/{cp_misalign}

fsq_op

New 128-bit variants of LOAD-FP and STORE-FP instructions are added, encoded with a new value for the funct3 width field.

MisalignQ_fsq_cg/{cp_misalign}

UDB Parameters: None.

Table 91. MisalignZca Instruction Coverpoints
Instruction c.lw c.lwsp c.ld c.ldsp c.sw c.swsp c.sd c.sdsp

Type

CL

CILS

CL

CILS

CS

CSS

CS

CSS

RV32

x

x

x

x

RV64

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

cp_misalign

x

x

x

x

x

x

x

x
Table 92. MisalignZca Normative Rules
Normative Rule Rule Text Coverpoints

MISALIGNED_LDST_FULLY_HW_SUPPORTED

misaligned loads and stores can be handled in hardware

{MisalignZca_c_lw_cg,MisalignZca_c_sw_cg}/{cp_misalign}

c-lw_op

C.LW loads a 32-bit value from memory into register rd′. It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register rs1′. It expands to lw rd′, offset(rs1′).

MisalignZca_c_lw_cg/{cp_misalign}

c-lwsp_op

C.LWSP loads a 32-bit value from memory into register rd. It computes an effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, x2. It expands to lw rd, offset(x2).

MisalignZca_c_lwsp_cg/{cp_misalign}

c-ld_op

C.LD is an RV64C-only instruction that loads a 64-bit value from memory into register rd′. It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register rs1′. It expands to ld rd′, offset(rs1′).

MisalignZca_c_ld_cg/{cp_misalign}

c-ldsp_op

C.LDSP is an RV64C-only instruction that loads a 64-bit value from memory into register rd. It computes its effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, x2. It expands to ld rd, offset(x2).

MisalignZca_c_ldsp_cg/{cp_misalign}

c-sw_op

C.SW stores a 32-bit value in register rs2′ to memory. It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register rs1′. It expands to sw rs2′, offset(rs1′).

MisalignZca_c_sw_cg/{cp_misalign}

c-swsp_op

C.SWSP stores a 32-bit value in register rs2 to memory. It computes an effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, x2. It expands to sw rs2, offset(x2).

MisalignZca_c_swsp_cg/{cp_misalign}

c-sd_op

C.SD is an RV64C-only instruction that stores a 64-bit value in register rs2′ to memory. It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register rs1′. It expands to sd rs2′, offset(rs1′).

MisalignZca_c_sd_cg/{cp_misalign}

c-sdsp_op

C.SDSP is an RV64C-only instruction that stores a 64-bit value in register rs2 to memory. It computes an effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, x2. It expands to sd rs2, offset(x2).

MisalignZca_c_sdsp_cg/{cp_misalign}

UDB Parameters: None.

Table 93. Misalign Coverpoint Definitions
Modified Coverpoint Bins Definition

cp_misalign

8

All 8 combinations of the three least significant bits of the address.

A.10.4. Zicclsm Misaligned Loads/Stores

The Zicclsm extension, defined in the RVA22 and RVA23 profiles, provides the following normative rule. The extension applies to privilege modes below M-mode (because the profiles apply to supervisor-mode execution environment), and requires that misaligned scalar and vector loads and stores to main memory either are handled in hardware or raise a misaligned exception that is handled by the execution environment. This is tested by Exceptions coverpoints that either return the expected value or throw a misaligned trap. Misaligned atomics are not part of Zicclsm, but are checked in {ExceptionsZaamo, ExceptionsZalrsc}/{cp_load_address_misaligned, cp_store_address_misaligned}.

Table 94. Zicclsm Normative Rules
Normative Rule Rule Text Coverpoints

zicclsm_op

Misaligned loads and stores to main memory regions with both the cacheability and coherence PMAs must be supported.

{ExceptionsS, ExceptionsU, ExceptionsZc, ExceptionsF, ExceptionsVls}/{cp_load_address_misaligned, cp_store_address_misaligned}

  • ExceptionsVls coverpoints need to be written.

  • update normative rule when tagged in profile and hyperlink is available

A.10.5. Zicond Conditional Instructions

Table 95. Zicond Instruction Coverpoints
Instruction czero.eqz czero.nez

Type

R

R

RV32

x

x

RV64

x

x

cp_asm_count

x

x

cp_rs1

x

x

cp_rs2

x

x

cp_rd

x

x

cp_rs1_edges

x

x

cp_rs2_edges

x

x

cr_rs1_rs2_edges

x

x

cmp_rs1_rs2

x

x

cmp_rd_rs1

x

x

cmp_rd_rs2

x

x

cmp_rd_rs1_rs2

x

x
Table 96. Zicond Normative Rules
Normative Rule Rule Text Coverpoints

czero-eqz_op

If rs2 contains the value zero, this instruction writes the value zero to rd. Otherwise, this instruction copies the contents of rs1 to rd.

Zicond_czero_eqz_cg/{cp_rs1, cp_rs2, cp_rd, cr_rs1_rs2_edges}

czero-nez_op

If rs2 contains a nonzero value, this instruction writes the value zero to rd. Otherwise, this instruction copies the contents of rs1 to rd.

Zicond_czero_nez_cg/{cp_rs1, cp_rs2, cp_rd, cr_rs1_rs2_edges}

UDB Parameters: None.

A.10.6. Zicntr Counters

Zicntr provides unprivileged read access to the cycle, time, and instret counters. Note that, like all other unprivileged tests, these tests are performed in M-mode. The ZicntrS and ZicntrU privileged tests exercise reading the counters in S-mode and U-mode, with control by mcounteren and scounteren CSRs. The Sm privileged tests exercise mcycle, minstret, and HPMs from M-mode.

Table 97. Zicntr Instruction Coverpoints
Instruction csrrs csrrc

Type

CSR

CSR

RV32

x

x

RV64

x

x

cp_cntr

x

x
Table 98. Zicntr Normative Rules
Normative Rule Rule Text Coverpoints

zihpm_op_sz_mode_acc

Zicntr_csrrs_cg/{cp_cntr}

zicntr_rdcycle_op

The RDCYCLE pseudoinstruction reads the low XLEN bits of the cycle CSR which holds a count of the number of clock cycles executed by the processor core on which the hart is running from an arbitrary start time in the past.

Zicntr_csrrs_cg/{cp_cntr}

zicntr_rdtime_op

The RDTIME pseudoinstruction reads the low XLEN bits of the \"time\" CSR, which counts wall-clock real time that has passed from an arbitrary start time in the past.

Zicntr_csrrs_cg/{cp_cntr}

zicntr_rdinstret_op

The RDINSTRET pseudoinstruction reads the low XLEN bits of the instret CSR, which counts the number of instructions retired by this hart from some arbitrary start point in the past.

Zicntr_csrrs_cg/{cp_cntr}
Table 99. Zicntr UDB Parameters
Parameter Description Coverpoint Effect

TIME_CSR_IMPLEMENTED

Whether or not a real hardware time CSR exists. Implementations can either provide a real CSR or emulate access at M-mode.

Possible values:

true:: time/timeh exists, and accessing it will not cause an IllegalInstruction trap

false:: time/timeh does not exist. Accessing the CSR will cause an IllegalInstruction trap or enter an unpredictable state, depending on TRAP_ON_UNIMPLEMENTED_CSR. Privileged software may emulate the time CSR, or may pass the exception to a lower level.

cp_cntr

Skip time and timeh if False

TODO: add normative rule for TIME_CSR_IMPLEMENTED UDB parameter referencing the following text from the priv spec:

` emulate this functionality on behalf of less-privileged modes in M-mode software. ` This rule is checked by the time bin of cp_cntr coverpoint.

Table 100. Zicntr Coverpoint Definition
Coverpoint Bins Definition

cp_cntr

3

Read each of the counters (cycle, time, instret) twice using csrrs rd, csr, x0 and check that the difference is exactly right for instret, or at least 1 for cycle, 0 for time (time may not increment between reads). For RV32, also check cycleh, timeh, instreth with the same definitions. Skip time and timeh if parameter TIME_CSR_IMPLEMENTED = False.

A.10.7. Zihpm Hardware Performance Monitors

Zihpm provides unprivileged read access to custom hardware performance monitor CSRs.

Table 101. Zihpm Instruction Coverpoints
Instruction csrrs csrrc

Type

CSR

CSR

RV32

x

x

RV64

x

x

cp_cntr

hpm

hpm
Table 102. Zihpm Normative Rules
Normative Rule Rule Text Coverpoints

zihpm_op_sz_mode_acc

Zihpm_csrrs_cg/{cp_cntr_hpm}

hpmcounter_op_sz_mode

The Zihpm extension comprises up to 29 additional unprivileged 64-bit hardware performance counters, hpmcounter3-hpmcounter31.

Zihpm_csrrs_cg/{cp_cntr_hpm}

UDB Parameters: None.

Table 103. Zihpm Coverpoint Definition
Coverpoint Bins Definition

cp_cntr_hpm

29

Read each of the HPMs twice and check that the difference is non-negative. For RV32, also check the high halves of each HPM.

Note that this coverpoint assumes that reading hpmcounter* never traps. See RISC-V ISA Manual Issue #2558 for discussion. There may not be a graceful way to certify Zihpm on an implementation that allows hpmcounter* reads to sometimes trap because unprivileged tests should not trap.

=== MCOUNTENABLE_EN, SCOUNTENABLE_EN, HCOUNTENABLE_EN parameters are exercised by ZicsrS/U/H cp_xcounteren_access_y tests (Table 170). COUNTINHIBIT_EN is exercised by Sm/cp_inhibit tests (Table 128). ===

A.10.8. Zihintpause Pause Hint

Table 104. Zihintpause Instruction Coverpoints
Instruction pause

Type

I

RV32

x

RV64

x

cp_asm_count

x
Table 105. Zihintpause Normative Rules
Normative Rule Rule Text Coverpoints

pause_op

The PAUSE instruction is a HINT that indicates the current hart’s rate of instruction retirement should be temporarily reduced or paused. The duration of its effect must be bounded and may be zero.

Zihintpause_pause_cg/cp_asm_count

UDB Parameters: None.

A.10.9. Zihintntl Non-temporal Locality Hint

A.10.10. ZihintntlZca Compressed Non-temporal Locality Hint

Zihintntl Instruction Coverpoints

Compressed Zihintntl instructions c.ntl.p1, c.ntl.pall, c.ntl.s1, and c.ntl.all are a subset of the c.add hints. They are tested by the Zca_c_hint_cg/cp_chint_add coverpoint, so require no additional coverpoints.

Table 106. ZihintntlZca Normative Rules
Normative Rule Rule Text Coverpoints

C-NTL-P1_op

If the C or Zca extension is provided, compressed variants of these HINTs are also provided: C.NTL.P1 is encoded as C.ADD x0, x2; C.NTL.PALL is encoded as C.ADD x0, x3; C.NTL.S1 is encoded as C.ADD x0, x4; and C.NTL.ALL is encoded as C.ADD x0, x5.

Zca_c_hint_cg/cp_chint_add

C-NTL-ALL_op

If the C or Zca extension is provided, compressed variants of these HINTs are also provided: C.NTL.P1 is encoded as C.ADD x0, x2; C.NTL.PALL is encoded as C.ADD x0, x3; C.NTL.S1 is encoded as C.ADD x0, x4; and C.NTL.ALL is encoded as C.ADD x0, x5.

Zca_c_hint_cg/cp_chint_add

C-NTL-PALL_op

If the C or Zca extension is provided, compressed variants of these HINTs are also provided: C.NTL.P1 is encoded as C.ADD x0, x2; C.NTL.PALL is encoded as C.ADD x0, x3; C.NTL.S1 is encoded as C.ADD x0, x4; and C.NTL.ALL is encoded as C.ADD x0, x5.

Zca_c_hint_cg/cp_chint_add

C-NTL-S1_op

If the C or Zca extension is provided, compressed variants of these HINTs are also provided: C.NTL.P1 is encoded as C.ADD x0, x2; C.NTL.PALL is encoded as C.ADD x0, x3; C.NTL.S1 is encoded as C.ADD x0, x4; and C.NTL.ALL is encoded as C.ADD x0, x5.

Zca_c_hint_cg/cp_chint_add

UDB Parameters: None.

A.10.11. Zicbom Cache Block Flush/Invalidate

A.10.12. Zicboz Cache Block Zero

A.10.13. Zicbop Cache Block Prefetch

A.10.14. Za64rs Max 64B Reservation Set

A.10.15. Zic64bZicboz 64B Cache Block Zero

A.11. V Vector Extension

Zic64bZicboz Instruction Coverpoints

The vector coverpoints are intended to be flexible to support the full V extension, the Zve* embedded vector extensions, and arbitrary mixes of supported vector length (VLEN), element lengths (SEWMIN, ELEN), and floating-point precisions.

The vector extension is huge. The testplan is partitioned into three unprivileged portions discussed here, and two privileged portions (ExceptionsV, SsstrictV) discussed in XREF.

The full V extension supports all selected element widths SEW={8, 16, 32, 64}. The vector coverage files and tests are organized by SEW. Thus, a DUT could handle any contiguous subset of SEW from SEWMIN to ELEN. For example, a DUT with SEWMIN=16 and ELEN=32 would support SEW={16, 32}.

The tests detect VLMAX and set the vector length accordingly, up to some configurable maximum VLEN (default 4096 bits, although the vector extension theoretically supports up to 65536). Therefore, there is no need for different test suites for different VLENs.

A.11.1. Vector File Organization

Listing 1 summarizes the structure of the coverpoint and test files for the vector extension. The unprivileged vector tests are organized by integer (Vx), load/store (Vls), and floating-point (Vf) types of instructions. Each applies to SEW=8, 16, 32, and/or 64. The ExceptionsV, V, and SsstrictV privileged tests are described in section XREF.

The vector tests are organized by XLEN=32 and XLEN=64 because the scalar registers behavior differs by XLEN. For example, vadd.vx with SEW=64 sign-extends XLEN=32 scalar registers but does not modify XLEN=64 scalar registers. For a given XLEN, the vector tests are organized by type (Vx/Vls/Vf) and SEW (8/16/32/64). Each directory contains a .S file for every vector instruction of that type [4]. Vector load/store instructions run with any SEW but also specify EEW as part of the instruction name. For example, vle8.v and vle16.v can both be executed in either SEW=8 or SEW=16, and the EMUL behavior is different between these modes. Therefore, all the load/store variants are included in all of Vls{8/16/32/64}.

Vx and Vf are separated because certain extensions such as Zve64x do not support floating-point. Vls could be lumped with Vx, but the coverpoints are so different that it is easier to define the tests separately, and facilitates just running integer vs. load/store tests during development.
Listing 1. Vector Organization
fcov
    unpriv
        Vx8_coverage.svh
        Vx16_coverage.svh
        Vx32_coverage.svh
        Vx64_coverage.svh
        Vls8_coverage.svh
        Vls16_coverage.svh
        Vls32_coverage.svh
        Vls64_coverage.svh
        Vf16_coverage.svh
        Vf32_coverage.svh
        Vf64_coverage.svh
      priv
        ExceptionsV_coverage.svh
        V_coverage.svh ***reorganize
        SsstrictV_coverage.svh
tests
    rv32
        Vx8
            vadd.vv.S
            vadd.vx.S
            vadd.vi.S
            vsub.vv.S
            ...
        Vx16
            vadd.vv.S
            ...
        Vx32
            vadd.vv.S
            ...
        Vx64
            vadd.vv.S
            ...
        Vls8
            vle8.v.S
            vle16.v.S
            vle32.v.S
            vle64.v.S
            vlseg2e8.v.S
            ...
        Vls16
            vle8.v.S
            ...
        Vls32
            vle8.v.S
            ...
        Vls64
            vle8.v.S
            ...
        Vf16
            vfadd.vv.S
            vfadd.vf.S
            vfwadd.vv.S
            vfsub.vv.S
            ...
        Vf32
            vfadd.vv.S
            ...
        Vf64
            vfadd.vv.S
            ...
    rv64
        Vx8
        Vx16
        Vx32
        Vx64
        Vls8
        Vls16
        Vls32
        Vls64
        Vf16
        Vf32
        Vf64
    priv
        ExceptionsV.S
        V.S *** reorganize
        SsstrictV.S

When an instruction’s EEW is not a supported SEW, the coverage files and tests exclude the instruction from testing. For example, vwadd.vv is not supported when SEW=32 and ELEN = 32 because it cannot widen to 64 bits.

The tests also account for unsupported register group overlap. For example, a widening add vwadd.wv v0, v2, v2 is unsupported because the source registers cannot be read with different EEWs. On the other hand vwadd.vv v0, v1, v8 with LMUL=1 is supported even though the destination vd=v0 widens to write [v0-v1], which overlaps with vs2=v1. The tests exercise all supported overlaps, but do not attempt any unsupported overlaps because the behavior is reserved and unpredictable.

A.11.2. Vector Configuration Parameters

The coverpoints and tests are parameterized by the minimum supported element width SEWMIN and the maximum supported element width ELEN. The coverpoints and tests exclude unsupported edge cases, such as widening to more than ELEN or using LMUL=1/8 with ELEN=32 but SEWMIN=8.

A.11.3. Vector Coverpoints

Running long vectors is computationally expensive, so only a subset of vectors tests run on multi-element vectors. Coverpoints for source and destination registers, edge values, etc. run on a vector length of vl = 1.

Table 107 defines the coverpoints used in vector instructions. Unless otherwise specified, each coverpoint uses vector length vl=1 and length multiplier LMUL=1, no mask (vm=1), and vstart=0. Hence, they act on exactly one vector element. For such coverpoints, instructions that require a mask use v0=0.

Table 107. Vector Coverpoint Definitions
Coverpoint # Bins Definition

Coverpoints acting on single element vl=1

cp_vd

32

All vector destination registers vd=0-31

cp_vs2

32

All vector source registers vs2=0-31

cp_vs1

32

All vector source registers vs1=0-31

cp_vs3

32

All vector source registers vs3=0-31

cp_rs1

32

All scalar registers rs1=0-31

cp_rs2

32

All scalar registers rs2=0-31

cp_imm_5bit

32

Signed immediate values -16 to +15

cmp_rs1_rs2

32

rs1 and rs2 are same register ID

cmp_vd_vs2

32

vd and vs2 are same register ID

cmp_vd_vs1

32

vd and vs1 are same register ID

cmp_vs2_vs1

32

vs2 and vs1 are same register ID

cmp_vs3_vs2

32

vs3 and vs2 are the same register ID

cmp_vd_vs1_vs2

32

vd and vs1 and vs2 are same register ID

cp_rs1_edges

9

0, 1, 2, -1, -2, most negative, most negative+1, most positive, most positive-1

cp_rs2_edges

5

0, 1, 2, -1, -2 (for strided vector load/store)

cp_fs1_edges

20

0, -1, -smallest subnorm, -inf, 1, 1+ulp, 0.5, 1.5, 2, 4, pi, 2^emax, largest normal, smallest normal, largest subnormal, subnormal with leading 1 in fraction, infinity, canonical quite NaN, noncanonical quiet NaN, signaling NaN with payload of 1

cp_vs2_edges

9 or 20

see cp_rs1_edges or cp_fs1_edges

cp_vs1_edges

9 or 20

see cp_rs1_edges

cr_vs2_vs1_edges

9^2 or 20^2

Cross-product of edges of vs2 and vs1

cr_vs2_rs1_edges

9*9

Cross-product of edges of vs2 and rs1

cr_vs2_fs1_edges

20*20

Cross-product of edges of vs2 and fs1

cr_vs2_imm_edges

9*9

Cross-product of edges of vs2 and imm={0, 1, 2, 14, 15, -1, -2, -15,-16}

cr_vxrm_vs2_vs1_edges

9*9*4

Cross-product of edges of vs2 and vs1 with vector rounding mode={rod, rdn, rne, rnu}

cr_vxrm_vs2_rs1_edges

9*9*4

See cr_vxrm_vs2_vs1_edges

cr_vxrm_vs2_imm_edges

9*9*4

See cr_vxrm_vs2_vs1_edges

cp_csr_frm

5*10

Floating-point rounding mode={rdn, rmm, rne, rtz, rup} with 10 random inputs per mode

cp_csr_fflags

5*2

Floating-point sets and clears all applicable flags

Coverpoints acting on multiple elements vl ≠ 1

cp_masking_edges

5

Mask edge cases v0=all 1s, all 0s, random, first VLMAX-1 ones, first VLMAX/2+1 ones; vl=VLMAX, vm=1 to mask, vma = random, vta = 0

cr_vl_lmul

7*3

Cross legal combinations of LMUL={1/2/4/8/f2/f4/f8} and vl={1, random, VLMAX}, while randomizing v0 mask value, vm, vta, vma.

cr_vtype_agnostic

4

Cross vta={0/1} and vma={0/1}. Random legal LMUL, random legal vl, vm=1, v0=random mask

cp_vxsat

2

vxsat={0, 1}. Hit by cr_vs2_vs1_edges so no tests needed.

cp_vl_0

1

vl=0. LMUL=1, no mask, vma=0, vta=1

As with other unprivileged testplans, an x in the spreadsheet indicates to use the coverpoint. Other values in the spreadsheet indicate a variant of the coverpoint:

  • nv0: Do not include v0 in the coverpoint. For example, cp_vd_nv0 means that the destination register vd does not include v0.

  • emul2: Only exercise even-numbered registers. For example cp_vs2_emul2 uses vs2={v0, v2, v4, …​v30}. For edge values, emul2 means the edge value is twice the width of SEW.

  • emul4/8: Similar to emul2

  • emulf2, emulf4, emulf8: edge values are 1/2, 1/4, or 1/8 the width of SEW. Used in extension instructions such as vsext.vf2.

  • u: Treat immediate as unsigned 0 to 31 rather than signed -16 to +15. For edge values, {0, 1, 2, 15, 16, 30, 31}.

  • eew1/mm: Mask instructions with 1-bit elements such as vmand.mm use at least vl=8 to operate on multi-bit masks.

  • wv: vs2 is double-width and uses emul2 for its edge values. vs1 is normal width.

  • wred: vs1 is double-width and uses emul2 for its edge values. vs2 is normal width.

  • wx: vs2 is double-width and uses emul2 for its edge values. rs1 is normal width.

  • wi/wiu: vs2 is double-width and uses emul2 for its edge values. immediate is 5 bit signed or unsigned.

  • lmul4max/emul4max: maximum LMUL/EMUL is 4 instead of 8. vwadd.vv uses lmul4max because it cannot accept LMUL=8 widened to 16. vlseg2e8.v uses emul4max because the number of segments * EMUL cannot exceed 8.

  • lmul2max/lmul1max/emul2max/emul1max: see lmul4max

  • lte30/…​/lte24: Register number is less than or equal to 30, …​, 24. Used for segmented load/store so segments won’t overflow the register file.

  • ls_e{8/16/32/64}: load/store edges with EEW=8,…​,64. Used to convert strided loads from elements to bytes.

  • ls: load/store edges instead of integer edges: vs2={0, random < 2*VLMAX}. rs2= {1, 2, -1, -2, 0}

  • f: floating-point edges instead of integer edges: *

  • cp_custom_*: custom coverpoint defined in the coverage file. See definitions for "CustomVx", "Vx_custom_definitions", "CustomVf", "CustomVls".

The coverpoints for each vector instruction are given in the following sections.

A.11.4. Vx

The Vx testplan is the same for SEW={8, 16, 32, 64}. Each SEW has its own coverage file (e.g. Vx8_coverages.svh) independent of XLEN, as well as tests that depend on XLEN (e.g. rv32/Vx8/vadd.vx.S).

Table 108. Vx Instruction Coverpoints
Instruction vadd.vv vadd.vx vadd.vi vwadd.vv vwadd.vx vwaddu.vv vwaddu.vx vwadd.wv vwadd.wx

Type

VVVM

VVXM

VVIM

VVVM

VVXM

VVVM

VVXM

VVVM

VVXM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

x

x

x

emul2

emul2

emul2

emul2

emul2

emul2

cp_vs2

x

x

x

x

x

x

x

emul2

emul2

cp_vs1

x

x

x

x

cp_rs1

x

x

x

x

cp_imm_5bit

x

cmp_vd_vs2

x

x

x

emul2

emul2

cmp_vd_vs1

x

cmp_vs1_vs2

x

x

x

cmp_vd_vs1_vs2

x

cp_vs2_edges

x

x

x

x

x

x

x

emul2

emul2

cp_vs1_edges

x

x

x

x

cr_vs2_vs1_edges

x

x

x

wv

cp_rs1_edges

x

x

x

x

cr_vs2_rs1_edges

x

x

x

wx

cr_vs2_imm_edges

x

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

x

x

x

lmul4max

lmul4max

lmul4max

lmul4max

lmul4max

lmul4max

cr_vtype_agnostic

x

x

x

lmul4max

lmul4max

lmul4max

lmul4max

lmul4max

lmul4max

cp_vl_0

x

x

x

x

x

x

x

x

x

cp_custom

wvv_all

wvx_all

wvv

wvx

wwv_all
Instruction vwaddu.wv vwaddu.wx vsub.vv vsub.vx vwsub.vv vwsub.vx vwsubu.vv vwsubu.vx vwsub.wv

Type

VVVM

VVXM

VVVM

VVXM

VVVM

VVXM

VVVM

VVXM

VVVM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

emul2

emul2

x

x

emul2

emul2

emul2

emul2

emul2

cp_vs2

emul2

emul2

x

x

x

x

x

x

emul2

cp_vs1

x

x

x

x

x

cp_rs1

x

x

x

x

cmp_vd_vs2

emul2

emul2

x

x

emul2

cmp_vd_vs1

x

cmp_vs1_vs2

x

x

x

cmp_vd_vs1_vs2

x

cp_vs2_edges

emul2

emul2

x

x

x

x

x

x

emul2

cp_vs1_edges

x

x

x

x

x

cr_vs2_vs1_edges

wv

x

x

x

wv

cp_rs1_edges

x

x

x

x

cr_vs2_rs1_edges

wx

x

x

x

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

lmul4max

lmul4max

x

x

lmul4max

lmul4max

lmul4max

lmul4max

lmul4max

cr_vtype_agnostic

lmul4max

lmul4max

x

x

lmul4max

lmul4max

lmul4max

lmul4max

lmul4max

cp_vl_0

x

x

x

x

x

x

x

x

x

cp_custom

wwv

wvv

wvx

wvv

wvx

wwv
Instruction vwsub.wx vwsubu.wv vwsubu.wx vrsub.vx vrsub.vi vzext.vf2 vzext.vf4 vzext.vf8 vsext.vf2

Type

VVXM

VVVM

VVXM

VVXM

VVIM

VVM

VVM

VVM

VVM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

emul2

emul2

emul2

x

x

x

x

x

x

cp_vs2

emul2

emul2

emul2

x

x

x

x

x

x

cp_vs1

x

cp_rs1

x

x

x

cp_imm_5bit

x

cmp_vd_vs2

emul2

emul2

emul2

x

x

cp_vs2_edges

emul2

emul2

emul2

x

x

emulf2

emulf4

emulf8

emulf2

cp_vs1_edges

x

cr_vs2_vs1_edges

wv

cp_rs1_edges

x

x

x

cr_vs2_rs1_edges

wx

wx

x

cr_vs2_imm_edges

x

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

lmul4max

lmul4max

lmul4max

x

x

x

x

x

x

cr_vtype_agnostic

lmul4max

lmul4max

lmul4max

x

x

x

x

x

x

cp_vl_0

x

x

x

x

x

x

x

x

x

cp_custom

wwv

vext2

vext4

vext8

vext2
Instruction vsext.vf4 vsext.vf8 vadc.vvm vadc.vxm vadc.vim vsbc.vvm vsbc.vxm vmadc.vvm vmadc.vxm

Type

VVM

VVM

VVVM

VVXM

VVIM

VVVM

VVXM

VVVM

VVXM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

x

x

nv0

nv0

nv0

nv0

nv0

x

x

cp_vs2

x

x

nv0

nv0

nv0

nv0

nv0

nv0

nv0

cp_vs1

nv0

nv0

nv0

cp_rs1

x

x

x

cp_imm_5bit

x

cmp_vd_vs2

nv0

nv0

nv0

nv0

nv0

cmp_vd_vs1

nv0

nv0

cmp_vs1_vs2

nv0

nv0

nv0

cmp_vd_vs1_vs2

nv0

nv0

cp_vs2_edges

emulf4

emulf8

x

x

x

x

x

x

x

cp_vs1_edges

x

x

x

cr_vs2_vs1_edges

x

x

x

cp_rs1_edges

x

x

x

cr_vs2_rs1_edges

x

x

x

cr_vs2_imm_edges

x

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

x

x

x

x

x

x

x

x

x

cr_vtype_agnostic

x

x

x

x

x

x

x

x

x

cp_vl_0

x

x

x

x

x

x

x

x

x

cp_custom

vext4

vext8

maskwrite_masked

maskwrite_masked
Instruction vmadc.vim vmadc.vv vmadc.vx vmadc.vi vmsbc.vvm vmsbc.vxm vmsbc.vv vmsbc.vx vand.vv

Type

VVIM

VVV

VVX

VVI

VVVM

VVXM

VVV

VVX

VVVM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

x

x

x

x

x

x

x

x

x

cp_vs2

nv0

x

x

x

nv0

nv0

x

x

x

cp_vs1

x

nv0

x

x

cp_rs1

x

x

x

cp_imm_5bit

x

x

cmp_vd_vs2

x

cmp_vd_vs1

x

cmp_vs1_vs2

x

nv0

x

x

cmp_vd_vs1_vs2

x

cp_vs2_edges

x

x

x

x

x

x

x

x

x

cp_vs1_edges

x

x

x

x

cr_vs2_vs1_edges

x

x

x

x

cp_rs1_edges

x

x

x

cr_vs2_rs1_edges

x

x

x

cr_vs2_imm_edges

x

x

cp_masking_edges

x

x

x

x

cr_vl_lmul

x

x

x

x

x

x

x

x

x

cr_vtype_agnostic

x

nomask

nomask

nomask

x

x

nomask

nomask

x

cp_vl_0

x

x

x

x

x

x

x

x

x

cp_custom

maskwrite_masked

maskwrite_unmasked

maskwrite_unmasked

maskwrite_unmasked

maskwrite_masked

maskwrite_masked

maskwrite_unmasked

maskwrite_unmasked
Instruction vand.vx vand.vi vor.vv vor.vx vor.vi vxor.vv vxor.vx vxor.vi vsll.vv

Type

VVXM

VVIM

VVVM

VVXM

VVIM

VVVM

VVXM

VVIM

VVVM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

x

x

x

x

x

x

x

x

x

cp_vs2

x

x

x

x

x

x

x

x

x

cp_vs1

x

x

x

cp_rs1

x

x

x

cp_imm_5bit

x

x

x

cmp_vd_vs2

x

x

x

x

x

x

x

x

x

cmp_vd_vs1

x

x

x

cmp_vs1_vs2

x

x

x

cmp_vd_vs1_vs2

x

x

x

cp_vs2_edges

x

x

x

x

x

x

x

x

x

cp_vs1_edges

x

x

x

cr_vs2_vs1_edges

x

x

x

cp_rs1_edges

x

x

x

cr_vs2_rs1_edges

x

x

x

cr_vs2_imm_edges

x

x

x

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

x

x

x

x

x

x

x

x

x

cr_vtype_agnostic

x

x

x

x

x

x

x

x

x

cp_vl_0

x

x

x

x

x

x

x

x

x

cp_custom

shift_vv
Instruction vsll.vx vsll.vi vsrl.vv vsrl.vx vsrl.vi vnsrl.wv vnsrl.wx vnsrl.wi vsra.vv

Type

VVXM

VVIM

VVVM

VVXM

VVIM

VVVM

VVXM

VVIM

VVVM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

x

x

x

x

x

x

x

x

x

cp_vs2

x

x

x

x

x

emul2

emul2

emul2

x

cp_vs1

x

x

x

cp_rs1

x

x

x

cp_imm_5bit

u

u

u

cmp_vd_vs2

x

x

x

x

x

x

cmp_vd_vs1

x

x

x

cmp_vs1_vs2

x

x

cmp_vd_vs1_vs2

x

x

cp_vs2_edges

x

x

x

x

x

emul2

emul2

emul2

x

cp_vs1_edges

x

x

x

cr_vs2_vs1_edges

x

wv

x

cp_rs1_edges

x

x

x

cr_vs2_rs1_edges

x

x

wx

cr_vs2_imm_edges

u

u

wiu

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

x

x

x

x

x

lmul4max

lmul4max

lmul4max

x

cr_vtype_agnostic

x

x

x

x

x

lmul4max

lmul4max

lmul4max

x

cp_vl_0

x

x

x

x

x

x

x

x

x

cp_custom

shift_vx

shift_vv

shift_vx

shift_wv

shift_wx

shift_wi

shift_vv
Instruction vsra.vx vsra.vi vnsra.wv vnsra.wx vnsra.wi vmseq.vv vmseq.vx vmseq.vi vmsne.vv

Type

VVXM

VVIM

VVVM

VVXM

VVIM

VVVM

VVXM

VVIM

VVVM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

x

x

x

x

x

x

x

x

x

cp_vs2

x

x

emul2

emul2

emul2

x

x

x

x

cp_vs1

x

x

x

cp_rs1

x

x

x

cp_imm_5bit

u

u

x

cmp_vd_vs2

x

x

cmp_vd_vs1

x

cmp_vs1_vs2

x

x

cp_vs2_edges

x

x

emul2

emul2

emul2

x

x

x

x

cp_vs1_edges

x

x

x

cr_vs2_vs1_edges

wv

x

x

cp_rs1_edges

x

x

x

cr_vs2_rs1_edges

x

wx

x

cr_vs2_imm_edges

u

wiu

x

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

x

x

lmul4max

lmul4max

lmul4max

x

x

x

x

cr_vtype_agnostic

x

x

lmul4max

lmul4max

lmul4max

x

x

x

x

cp_vl_0

x

x

x

x

x

x

x

x

x

cp_custom

shift_vx

shift_wv

shift_wx

shift_wi

maskwrite_masked

maskwrite_masked

maskwrite_masked

maskwrite_masked
Instruction vmsne.vx vmsne.vi vmslt.vv vmslt.vx vmsltu.vv vmsltu.vx vmsle.vv vmsle.vx vmsle.vi

Type

VVXM

VVIM

VVVM

VVXM

VVVM

VVXM

VVVM

VVXM

VVIM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

x

x

x

x

x

x

x

x

x

cp_vs2

x

x

x

x

x

x

x

x

x

cp_vs1

x

x

x

cp_rs1

x

x

x

x

cp_imm_5bit

x

x

cmp_vs1_vs2

x

x

x

cp_vs2_edges

x

x

x

x

x

x

x

x

x

cp_vs1_edges

x

x

x

cr_vs2_vs1_edges

x

x

x

cp_rs1_edges

x

x

x

x

cr_vs2_rs1_edges

x

x

x

x

cr_vs2_imm_edges

x

x

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

x

x

x

x

x

x

x

x

x

cr_vtype_agnostic

x

x

x

x

x

x

x

x

x

cp_vl_0

x

x

x

x

x

x

x

x

x

cp_custom

maskwrite_masked

maskwrite_masked

maskwrite_masked

maskwrite_masked

maskwrite_masked

maskwrite_masked

maskwrite_masked

maskwrite_masked

maskwrite_masked
Instruction vmsleu.vv vmsleu.vx vmsleu.vi vmsgt.vx vmsgt.vi vmsgtu.vx vmsgtu.vi vmin.vv vmin.vx

Type

VVVM

VVXM

VVIM

VVXM

VVIM

VVXM

VVIM

VVVM

VVXM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

x

x

x

x

x

x

x

x

x

cp_vs2

x

x

x

x

x

x

x

x

x

cp_vs1

x

x

cp_rs1

x

x

x

x

cp_imm_5bit

x

x

x

cmp_vd_vs2

x

x

cmp_vd_vs1

x

cmp_vs1_vs2

x

x

cmp_vd_vs1_vs2

x

cp_vs2_edges

x

x

x

x

x

x

x

x

x

cp_vs1_edges

x

x

cr_vs2_vs1_edges

x

x

cp_rs1_edges

x

x

x

x

cr_vs2_rs1_edges

x

x

x

x

cr_vs2_imm_edges

x

x

x

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

x

x

x

x

x

x

x

x

x

cr_vtype_agnostic

x

x

x

x

x

x

x

x

x

cp_vl_0

x

x

x

x

x

x

x

x

x

cp_custom

maskwrite_masked

maskwrite_masked

maskwrite_masked

maskwrite_masked

maskwrite_masked

maskwrite_masked

maskwrite_masked
Instruction vminu.vv vminu.vx vmax.vv vmax.vx vmaxu.vv vmaxu.vx vmul.vv vmul.vx vmulh.vv

Type

VVVM

VVXM

VVVM

VVXM

VVVM

VVXM

VVVM

VVXM

VVVM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

x

x

x

x

x

x

x

x

x

cp_vs2

x

x

x

x

x

x

x

x

x

cp_vs1

x

x

x

x

x

cp_rs1

x

x

x

x

cmp_vd_vs2

x

x

x

x

x

x

x

x

x

cmp_vd_vs1

x

x

x

x

x

cmp_vs1_vs2

x

x

x

x

x

cmp_vd_vs1_vs2

x

x

x

x

x

cp_vs2_edges

x

x

x

x

x

x

x

x

x

cp_vs1_edges

x

x

x

x

x

cr_vs2_vs1_edges

x

x

x

x

x

cp_rs1_edges

x

x

x

x

cr_vs2_rs1_edges

x

x

x

x

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

x

x

x

x

x

x

x

x

x

cr_vtype_agnostic

x

x

x

x

x

x

x

x

x

cp_vl_0

x

x

x

x

x

x

x

x

x
Instruction vmulh.vx vmulhu.vv vmulhu.vx vmulhsu.vv vmulhsu.vx vwmul.vv vwmul.vx vwmulu.vv vwmulu.vx

Type

VVXM

VVVM

VVXM

VVVM

VVXM

VVVM

VVXM

VVVM

VVXM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

x

x

x

x

x

emul2

emul2

emul2

emul2

cp_vs2

x

x

x

x

x

x

x

x

x

cp_vs1

x

x

x

x

cp_rs1

x

x

x

x

x

cmp_vd_vs2

x

x

x

x

x

cmp_vd_vs1

x

x

cmp_vs1_vs2

x

x

x

x

cmp_vd_vs1_vs2

x

x

cp_vs2_edges

x

x

x

x

x

x

x

x

x

cp_vs1_edges

x

x

x

x

cr_vs2_vs1_edges

x

x

x

x

cp_rs1_edges

x

x

x

x

x

cr_vs2_rs1_edges

x

x

x

x

x

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

x

x

x

x

x

lmul4max

lmul4max

lmul4max

lmul4max

cr_vtype_agnostic

x

x

x

x

x

lmul4max

lmul4max

lmul4max

lmul4max

cp_vl_0

x

x

x

x

x

x

x

x

x

cp_custom

wvv

wvx

wvv

wvx
Instruction vwmulsu.vv vwmulsu.vx vdiv.vv vdiv.vx vdivu.vv vdivu.vx vrem.vv vrem.vx vremu.vv

Type

VVVM

VVXM

VVVM

VVXM

VVVM

VVXM

VVVM

VVXM

VVVM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

emul2

emul2

x

x

x

x

x

x

x

cp_vs2

x

x

x

x

x

x

x

x

x

cp_vs1

x

x

x

x

x

cp_rs1

x

x

x

x

cmp_vd_vs2

x

x

x

x

x

x

x

cmp_vd_vs1

x

x

x

x

cmp_vs1_vs2

x

x

x

x

x

cmp_vd_vs1_vs2

x

x

x

x

cp_vs2_edges

x

x

x

x

x

x

x

x

x

cp_vs1_edges

x

x

x

x

x

cr_vs2_vs1_edges

x

x

x

x

x

cp_rs1_edges

x

x

x

x

cr_vs2_rs1_edges

x

x

x

x

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

lmul4max

lmul4max

x

x

x

x

x

x

x

cr_vtype_agnostic

lmul4max

lmul4max

x

x

x

x

x

x

x

cp_vl_0

x

x

x

x

x

x

x

x

x

cp_custom

wvv

wvx
Instruction vremu.vx vmacc.vv vmacc.vx vnmsac.vv vnmsac.vx vmadd.vv vmadd.vx vnmsub.vv vnmsub.vx

Type

VVXM

VVVMR

VXVM

VVVMR

VXVM

VVVMR

VXVM

VVVMR

VXVM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

x

x

x

x

x

x

x

x

x

cp_vs2

x

x

x

x

x

x

x

x

x

cp_vs1

x

x

x

x

cp_rs1

x

x

x

x

x

cmp_vd_vs2

x

x

x

x

x

x

x

x

x

cmp_vd_vs1

x

x

x

x

cmp_vs1_vs2

x

x

x

x

cmp_vd_vs1_vs2

x

x

x

x

cp_vs2_edges

x

x

x

x

x

x

x

x

x

cp_vs1_edges

x

x

x

x

cr_vs2_vs1_edges

x

x

x

x

cp_rs1_edges

x

x

x

x

x

cr_vs2_rs1_edges

x

x

x

x

x

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

x

x

x

x

x

x

x

x

x

cr_vtype_agnostic

x

x

x

x

x

x

x

x

x

cp_vl_0

x

x

x

x

x

x

x

x

x
Instruction vwmacc.vv vwmacc.vx vwmaccu.vv vwmaccu.vx vwmaccsu.vv vwmaccsu.vx vwmaccus.vx vmerge.vvm vmerge.vxm

Type

VVVMR

VXVM

VVVMR

VXVM

VVVMR

VXVM

VXVM

VVVM

VVXM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

emul2

emul2

emul2

emul2

emul2

emul2

emul2

nv0

nv0

cp_vs2

x

x

x

x

x

x

x

nv0

nv0

cp_vs1

x

x

x

nv0

cp_rs1

x

x

x

x

x

cmp_vd_vs2

nv0

nv0

cmp_vd_vs1

nv0

cmp_vs1_vs2

x

x

x

nv0

cmp_vd_vs1_vs2

nv0

cp_vs2_edges

x

x

x

x

x

x

x

x

x

cp_vs1_edges

x

x

x

x

cr_vs2_vs1_edges

x

x

x

x

cp_rs1_edges

x

x

x

x

x

cr_vs2_rs1_edges

x

x

x

x

x

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

lmul4max

lmul4max

lmul4max

lmul4max

lmul4max

lmul4max

lmul4max

x

x

cr_vtype_agnostic

lmul4max

lmul4max

lmul4max

lmul4max

lmul4max

lmul4max

lmul4max

x

x

cp_vl_0

x

x

x

x

x

x

x

x

x

cp_custom

wvv

wvx

wvv

wvx

wvv

wvx

wvx
Instruction vmerge.vim vmv.v.v vmv.v.x vmv.v.i vsadd.vv vsadd.vx vsadd.vi vsaddu.vv vsaddu.vx

Type

VVIM

VVR

VX

VI

VVVM

VVXM

VVIM

VVVM

VVXM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

nv0

x

x

x

x

x

x

x

x

cp_vs2

nv0

x

x

x

x

x

cp_vs1

x

x

x

cp_rs1

x

x

x

cp_imm_5bit

x

x

x

cmp_vd_vs2

nv0

x

x

x

x

x

cmp_vd_vs1

x

x

x

cmp_vs1_vs2

x

x

cmp_vd_vs1_vs2

x

x

cp_vs2_edges

x

x

x

x

x

x

cp_vs1_edges

x

x

x

cr_vs2_vs1_edges

x

x

cp_rs1_edges

x

x

x

cr_vs2_rs1_edges

x

x

cr_vs2_imm_edges

x

x

cp_masking_edges

x

x

x

x

x

x

cr_vl_lmul

x

x

x

x

x

x

x

x

x

cr_vtype_agnostic

x

nomask

nomask

nomask

x

x

x

x

x

cp_vl_0

x

x

x

x

x

x

x

x

x
Instruction vsaddu.vi vssub.vv vssub.vx vssubu.vv vssubu.vx vaadd.vv vaadd.vx vaaddu.vv vaaddu.vx

Type

VVIM

VVVM

VVXM

VVVM

VVXM

VVVM

VVXM

VVVM

VVXM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

x

x

x

x

x

x

x

x

x

cp_vs2

x

x

x

x

x

x

x

x

x

cp_vs1

x

x

x

x

cp_rs1

x

x

x

x

cp_imm_5bit

x

cmp_vd_vs2

x

x

x

x

x

x

x

x

x

cmp_vd_vs1

x

x

x

x

cmp_vs1_vs2

x

x

x

x

cmp_vd_vs1_vs2

x

x

x

x

cp_vs2_edges

x

x

x

x

x

x

x

x

x

cp_vs1_edges

x

x

x

x

cr_vs2_vs1_edges

x

x

x

x

cr_vxrm_vs2_vs1_edges

x

x

cp_rs1_edges

x

x

x

x

cr_vs2_rs1_edges

x

x

x

x

cr_vxrm_vs2_rs1_edges

x

x

cr_vs2_imm_edges

x

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

x

x

x

x

x

x

x

x

x

cr_vtype_agnostic

x

x

x

x

x

x

x

x

x

cp_vl_0

x

x

x

x

x

x

x

x

x
Instruction vasub.vv vasub.vx vasubu.vv vasubu.vx vsmul.vv vsmul.vx vssrl.vv vssrl.vx vssrl.vi

Type

VVVM

VVXM

VVVM

VVXM

VVVM

VVXM

VVVM

VVXM

VVIM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

x

x

x

x

x

x

x

x

x

cp_vs2

x

x

x

x

x

x

x

x

x

cp_vs1

x

x

x

x

cp_rs1

x

x

x

x

cp_imm_5bit

u

cmp_vd_vs2

x

x

x

x

x

x

x

x

x

cmp_vd_vs1

x

x

x

x

cmp_vs1_vs2

x

x

x

x

cmp_vd_vs1_vs2

x

x

x

x

cp_vs2_edges

x

x

x

x

x

x

x

x

x

cp_vs1_edges

x

x

x

x

cr_vs2_vs1_edges

x

x

x

x

cr_vxrm_vs2_vs1_edges

x

x

x

x

cp_rs1_edges

x

x

x

x

cr_vs2_rs1_edges

x

x

x

x

cr_vxrm_vs2_rs1_edges

x

x

x

x

cr_vs2_imm_edges

u

cr_vxrm_vs2_imm_edges

x

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

x

x

x

x

x

x

x

x

x

cr_vtype_agnostic

x

x

x

x

x

x

x

x

x

cp_vl_0

x

x

x

x

x

x

x

x

x

cp_custom

shift_vv

shift_vx
Instruction vssra.vv vssra.vx vssra.vi vnclip.wv vnclip.wx vnclip.wi vnclipu.wv vnclipu.wx vnclipu.wi

Type

VVVM

VVXM

VVIM

VVVM

VVXM

VVIM

VVVM

VVXM

VVIM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

x

x

x

x

x

x

x

x

x

cp_vs2

x

x

x

emul2

emul2

emul2

emul2

emul2

emul2

cp_vs1

x

x

x

cp_rs1

x

x

x

cp_imm_5bit

u

u

u

cmp_vd_vs2

x

x

x

cmp_vd_vs1

x

x

x

cmp_vs1_vs2

x

cmp_vd_vs1_vs2

x

cp_vs2_edges

x

x

x

emul2

emul2

emul2

emul2

emul2

emul2

cp_vs1_edges

x

x

x

cr_vs2_vs1_edges

x

wv

wv

cr_vxrm_vs2_vs1_edges

x

wv

wv

cp_rs1_edges

x

x

x

cr_vs2_rs1_edges

x

wx

wx

cr_vxrm_vs2_rs1_edges

x

wx

wx

cr_vs2_imm_edges

u

wiu

wiu

cr_vxrm_vs2_imm_edges

x

wi

wi

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

x

x

x

lmul4max

lmul4max

lmul4max

lmul4max

lmul4max

lmul4max

cr_vtype_agnostic

x

x

x

lmul4max

lmul4max

lmul4max

lmul4max

lmul4max

lmul4max

cp_vl_0

x

x

x

x

x

x

x

x

x

cp_custom

shift_vv

shift_vx

shift_wv

shift_wx

shift_wi

shift_wv

shift_wx

shift_wi
Instruction vredsum.vs vwredsum.vs vwredsumu.vs vredmax.vs vredmaxu.vs vredmin.vs vredminu.vs vredand.vs vredor.vs

Type

VVVM

VVVM

VVVM

VVVM

VVVM

VVVM

VVVM

VVVM

VVVM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

x

emul2

emul2

x

x

x

x

x

x

cp_vs2

x

x

x

x

x

x

x

x

x

cp_vs1

x

emul2

emul2

x

x

x

x

x

x

cmp_vd_vs2

x

x

x

x

x

x

x

cmp_vd_vs1

x

emul2

emul2

x

x

x

x

x

x

cmp_vs1_vs2

x

x

x

x

x

x

x

cmp_vd_vs1_vs2

x

x

x

x

x

x

x

cp_vs2_edges

x

x

x

x

x

x

x

x

x

cp_vs1_edges

x

emul2

emul2

x

x

x

x

x

x

cr_vs2_vs1_edges

x

wred

wred

x

x

x

x

x

x

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

x

lmul4max

lmul4max

x

x

x

x

x

x

cr_vtype_agnostic

x

lmul4max

lmul4max

x

x

x

x

x

x

cp_vl_0

x

x

x

x

x

x

x

x

x

cp_custom

red

wred

wred

red

red

red

red

red

red
Instruction vredxor.vs vmand.mm vmnand.mm vmandn.mm vmxor.mm vmor.mm vmnor.mm vmorn.mm vmxnor.mm

Type

VVVM

VVV

VVV

VVV

VVV

VVV

VVV

VVV

VVV

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

x

x

x

x

x

x

x

x

x

cp_vs2

x

x

x

x

x

x

x

x

x

cp_vs1

x

x

x

x

x

x

x

x

x

cmp_vd_vs2

x

x

x

x

x

x

x

x

x

cmp_vd_vs1

x

x

x

x

x

x

x

x

x

cmp_vs1_vs2

x

x

x

x

x

x

x

x

x

cmp_vd_vs1_vs2

x

x

x

x

x

x

x

x

x

cp_vs2_edges

x

eew1

eew1

eew1

eew1

eew1

eew1

eew1

eew1

cp_vs1_edges

x

eew1

eew1

eew1

eew1

eew1

eew1

eew1

eew1

cr_vs2_vs1_edges

x

mm

mm

mm

mm

mm

mm

mm

mm

cp_masking_edges

x

cr_vl_lmul

x

x

x

x

x

x

x

x

x

cr_vtype_agnostic

x

nomask

nomask

nomask

nomask

nomask

nomask

nomask

nomask

cp_vl_0

x

x

x

x

x

x

x

x

x

cp_custom

red

maskwrite_unmasked

maskwrite_unmasked

maskwrite_unmasked

maskwrite_unmasked

maskwrite_unmasked

maskwrite_unmasked

maskwrite_unmasked

maskwrite_unmasked
Instruction vcpop.m vfirst.m vmsbf.m vmsif.m vmsof.m viota.m vid.v vmv.x.s vmv.s.x

Type

XVM

XVM

VVM

VVM

VVM

VVM

VM

XV

VX

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

x

x

x

x

x

x

cp_rd

x

x

x

cp_vs2

x

x

x

x

x

x

x

cp_rs1

x

cp_vs2_edges

eew1

eew1

eew1

eew1

eew1

eew1

x

cp_rs1_edges

x

cp_masking_edges

x

x

x

x

x

x

x

cr_vl_lmul

x

x

x

x

x

x

x

x

x

cr_vtype_agnostic

x

x

x

x

x

x

x

nomask

nomask

cp_vl_0

x

x

x

x

x

x

x

x

x

cp_custom

gprwrite

gprwrite

maskwrite_unmasked

maskwrite_unmasked

maskwrite_unmasked

vmv_x_s

vmv_s_x
Instruction vslideup.vx vslideup.vi vslidedown.vx vslidedown.vi vslide1up.vx vslide1down.vx vrgather.vv vrgather.vx vrgather.vi

Type

VVXM

VVIM

VVXM

VVIM

VVXM

VVXM

VVVM

VVXM

VVIM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

x

x

x

x

x

x

x

x

x

cp_vs2

x

x

x

x

x

x

x

x

x

cp_vs1

x

cp_rs1

x

x

x

x

x

cp_imm_5bit

u

u

u

cmp_vd_vs2

x

x

x

cmp_vs1_vs2

x

cp_vs2_edges

x

x

x

x

x

x

x

x

x

cp_vs1_edges

x

cr_vs2_vs1_edges

x

cp_rs1_edges

x

x

x

x

x

cr_vs2_rs1_edges

x

x

x

x

x

cr_vs2_imm_edges

u

u

u

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

x

x

x

x

x

x

x

x

x

cr_vtype_agnostic

x

x

x

x

x

x

x

x

x

cp_vl_0

x

x

x

x

x

x

x

x

x

cp_custom

vindexVX

vindexVV

vindexVX
Instruction vrgatherei16.vv vcompress.vm vmv1r.v vmv2r.v vmv4r.v vmv8r.v

Type

VVVM

VVV

VV

VV

VV

VV

RV32

x

x

x

x

x

x

RV64

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

cp_vd

x

x

x

emul2

emul4

emul8

cp_vs2

x

x

x

emul2

emul4

emul8

cp_vs1

x

x

cmp_vd_vs2

x

emul2

emul4

emul8

cmp_vs1_vs2

x

cp_vs2_edges

x

x

cp_vs1_edges

x

x

cr_vs2_vs1_edges

x

x

cp_masking_edges

x

cr_vl_lmul

x

x

x

x

x

x

cr_vtype_agnostic

x

nomask

nomask

nomask

nomask

nomask

cp_vl_0

x

x

x

x

x

x

cp_custom

vindexVV

A.11.5. Vls

Table 109. Vls Instruction Coverpoints
Instruction vle8.v vle16.v vle32.v vle64.v vlseg2e8.v vlseg2e16.v vlseg2e32.v vlseg2e64.v vlseg3e8.v

Type

VXM

VXM

VXM

VXM

VXM

VXM

VXM

VXM

VXM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

x

x

x

x

lte30

lte30

lte30

lte30

lte29

cp_rs1

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

e8

e16

e32

e64

e8_emul4max

e16_emul4max

e32_emul4max

e64_emul4max

e8_emul2max

cr_vtype_agnostic

e8

e16

e32

e64

e8_emul4max

e16_emul4max

e32_emul4max

e64_emul4max

e8_emul2max

cp_vl_0

x

x

x

x

x

x

x

x

x
Instruction vlseg3e16.v vlseg3e32.v vlseg3e64.v vlseg4e8.v vlseg4e16.v vlseg4e32.v vlseg4e64.v vlseg5e8.v vlseg5e16.v

Type

VXM

VXM

VXM

VXM

VXM

VXM

VXM

VXM

VXM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

lte29

lte29

lte29

lte28

lte28

lte28

lte28

lte27

lte27

cp_rs1

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

e16_emul2max

e32_emul2max

e64_emul2max

e8_emul2max

e16_emul2max

e32_emul2max

e64_emul2max

e8_emul1max

e16_emul1max

cr_vtype_agnostic

e16_emul2max

e32_emul2max

e64_emul2max

e8_emul2max

e16_emul2max

e32_emul2max

e64_emul2max

e8_emul1max

e16_emul1max

cp_vl_0

x

x

x

x

x

x

x

x

x
Instruction vlseg5e32.v vlseg5e64.v vlseg6e8.v vlseg6e16.v vlseg6e32.v vlseg6e64.v vlseg7e8.v vlseg7e16.v vlseg7e32.v

Type

VXM

VXM

VXM

VXM

VXM

VXM

VXM

VXM

VXM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

lte27

lte27

lte26

lte26

lte26

lte26

lte25

lte25

lte25

cp_rs1

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

cr_vtype_agnostic

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

cp_vl_0

x

x

x

x

x

x

x

x

x
Instruction vlseg7e64.v vlseg8e8.v vlseg8e16.v vlseg8e32.v vlseg8e64.v vle8ff.v vle16ff.v vle32ff.v vle64ff.v

Type

VXM

VXM

VXM

VXM

VXM

VXM

VXM

VXM

VXM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

lte25

lte24

lte24

lte24

lte24

x

x

x

x

cp_rs1

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8

e16

e32

e64

cr_vtype_agnostic

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8

e16

e32

e64

cp_vl_0

x

x

x

x

x

x

x

x

x
Instruction vlseg2e8ff.v vlseg2e16ff.v vlseg2e32ff.v vlseg2e64ff.v vlseg3e8ff.v vlseg3e16ff.v vlseg3e32ff.v vlseg3e64ff.v vlseg4e8ff.v

Type

VXM

VXM

VXM

VXM

VXM

VXM

VXM

VXM

VXM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

lte30

lte30

lte30

lte30

lte29

lte29

lte29

lte29

lte28

cp_rs1

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

e8_emul4max

e16_emul4max

e32_emul4max

e64_emul4max

e8_emul2max

e16_emul2max

e32_emul2max

e64_emul2max

e8_emul2max

cr_vtype_agnostic

e8_emul4max

e16_emul4max

e32_emul4max

e64_emul4max

e8_emul2max

e16_emul2max

e32_emul2max

e64_emul2max

e8_emul2max

cp_vl_0

x

x

x

x

x

x

x

x

x
Instruction vlseg4e16ff.v vlseg4e32ff.v vlseg4e64ff.v vlseg5e8ff.v vlseg5e16ff.v vlseg5e32ff.v vlseg5e64ff.v vlseg6e8ff.v vlseg6e16ff.v

Type

VXM

VXM

VXM

VXM

VXM

VXM

VXM

VXM

VXM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

lte28

lte28

lte28

lte27

lte27

lte27

lte27

lte26

lte26

cp_rs1

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

e16_emul2max

e32_emul2max

e64_emul2max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

cr_vtype_agnostic

e16_emul2max

e32_emul2max

e64_emul2max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

cp_vl_0

x

x

x

x

x

x

x

x

x
Instruction vlseg6e32ff.v vlseg6e64ff.v vlseg7e8ff.v vlseg7e16ff.v vlseg7e32ff.v vlseg7e64ff.v vlseg8e8ff.v vlseg8e16ff.v vlseg8e32ff.v

Type

VXM

VXM

VXM

VXM

VXM

VXM

VXM

VXM

VXM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

lte26

lte26

lte25

lte25

lte25

lte25

lte24

lte24

lte24

cp_rs1

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

cr_vtype_agnostic

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

cp_vl_0

x

x

x

x

x

x

x

x

x
Instruction vlseg8e64ff.v vlse8.v vlse16.v vlse32.v vlse64.v vlsseg2e8.v vlsseg2e16.v vlsseg2e32.v vlsseg2e64.v

Type

VXM

VXXM

VXXM

VXXM

VXXM

VXXM

VXXM

VXXM

VXXM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

lte24

x

x

x

x

lte30

lte30

lte30

lte30

cp_rs1

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

cp_rs2

x

x

x

x

x

x

x

x

cp_rs2_edges

ls_e8

ls_e16

ls_e32

ls_e64

ls_e8

ls_e16

ls_e32

ls_e64

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

e64_emul1max

e8

e16

e32

e64

e8_emul4max

e16_emul4max

e32_emul4max

e64_emul4max

cr_vtype_agnostic

e64_emul1max

e8

e16

e32

e64

e8_emul4max

e16_emul4max

e32_emul4max

e64_emul4max

cp_vl_0

x

x

x

x

x

x

x

x

x
Instruction vlsseg3e8.v vlsseg3e16.v vlsseg3e32.v vlsseg3e64.v vlsseg4e8.v vlsseg4e16.v vlsseg4e32.v vlsseg4e64.v vlsseg5e8.v

Type

VXXM

VXXM

VXXM

VXXM

VXXM

VXXM

VXXM

VXXM

VXXM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

lte29

lte29

lte29

lte29

lte28

lte28

lte28

lte28

lte27

cp_rs1

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

cp_rs2

x

x

x

x

x

x

x

x

x

cp_rs2_edges

ls_e8

ls_e16

ls_e32

ls_e64

ls_e8

ls_e16

ls_e32

ls_e64

ls_e8

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

e8_emul2max

e16_emul2max

e32_emul2max

e64_emul2max

e8_emul2max

e16_emul2max

e32_emul2max

e64_emul2max

e8_emul1max

cr_vtype_agnostic

e8_emul2max

e16_emul2max

e32_emul2max

e64_emul2max

e8_emul2max

e16_emul2max

e32_emul2max

e64_emul2max

e8_emul1max

cp_vl_0

x

x

x

x

x

x

x

x

x
Instruction vlsseg5e16.v vlsseg5e32.v vlsseg5e64.v vlsseg6e8.v vlsseg6e16.v vlsseg6e32.v vlsseg6e64.v vlsseg7e8.v vlsseg7e16.v

Type

VXXM

VXXM

VXXM

VXXM

VXXM

VXXM

VXXM

VXXM

VXXM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

lte27

lte27

lte27

lte26

lte26

lte26

lte26

lte25

lte25

cp_rs1

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

cp_rs2

x

x

x

x

x

x

x

x

x

cp_rs2_edges

ls_e16

ls_e32

ls_e64

ls_e8

ls_e16

ls_e32

ls_e64

ls_e8

ls_e16

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

cr_vtype_agnostic

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

cp_vl_0

x

x

x

x

x

x

x

x

x
Instruction vlsseg7e32.v vlsseg7e64.v vlsseg8e8.v vlsseg8e16.v vlsseg8e32.v vlsseg8e64.v vluxei8.v vluxei16.v vluxei32.v

Type

VXXM

VXXM

VXXM

VXXM

VXXM

VXXM

VXVM

VXVM

VXVM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

lte25

lte25

lte24

lte24

lte24

lte24

x

x

x

cp_vs2

x

x

x

cp_vs2_edges

ls

ls

ls

cmp_vd_vs2

sew_lte_8

sew_lte_16

sew_lte_32

cp_rs1

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

cp_rs2

x

x

x

x

x

x

cp_rs2_edges

ls_e32

ls_e64

ls_e8

ls_e16

ls_e32

ls_e64

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8

e16

e32

cr_vtype_agnostic

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8

e16

e32

cp_vl_0

x

x

x

x

x

x

x

x

x
Instruction vluxei64.v vluxseg2ei8.v vluxseg2ei16.v vluxseg2ei32.v vluxseg2ei64.v vluxseg3ei8.v vluxseg3ei16.v vluxseg3ei32.v vluxseg3ei64.v

Type

VXVM

VXVM

VXVM

VXVM

VXVM

VXVM

VXVM

VXVM

VXVM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

x

lte30

lte30

lte30

lte30

lte29

lte29

lte29

lte29

cp_vs2

x

x

x

x

x

x

x

x

x

cp_vs2_edges

ls

ls

ls

ls

ls

ls

ls

ls

ls

cmp_vd_vs2

sew_lte_64

cp_rs1

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

e64

e8_emul4max

e16_emul4max

e32_emul4max

e64_emul4max

e8_emul2max

e16_emul2max

e32_emul2max

e64_emul2max

cr_vtype_agnostic

e64

e8_emul4max

e16_emul4max

e32_emul4max

e64_emul4max

e8_emul2max

e16_emul2max

e32_emul2max

e64_emul2max

cp_vl_0

x

x

x

x

x

x

x

x

x
Instruction vluxseg4ei8.v vluxseg4ei16.v vluxseg4ei32.v vluxseg4ei64.v vluxseg5ei8.v vluxseg5ei16.v vluxseg5ei32.v vluxseg5ei64.v vluxseg6ei8.v

Type

VXVM

VXVM

VXVM

VXVM

VXVM

VXVM

VXVM

VXVM

VXVM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

lte28

lte28

lte28

lte28

lte27

lte27

lte27

lte27

lte26

cp_vs2

x

x

x

x

x

x

x

x

x

cp_vs2_edges

ls

ls

ls

ls

ls

ls

ls

ls

ls

cp_rs1

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

e8_emul2max

e16_emul2max

e32_emul2max

e64_emul2max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

cr_vtype_agnostic

e8_emul2max

e16_emul2max

e32_emul2max

e64_emul2max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

cp_vl_0

x

x

x

x

x

x

x

x

x
Instruction vluxseg6ei16.v vluxseg6ei32.v vluxseg6ei64.v vluxseg7ei8.v vluxseg7ei16.v vluxseg7ei32.v vluxseg7ei64.v vluxseg8ei8.v vluxseg8ei16.v

Type

VXVM

VXVM

VXVM

VXVM

VXVM

VXVM

VXVM

VXVM

VXVM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

lte26

lte26

lte26

lte25

lte25

lte25

lte25

lte24

lte24

cp_vs2

x

x

x

x

x

x

x

x

x

cp_vs2_edges

ls

ls

ls

ls

ls

ls

ls

ls

ls

cp_rs1

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

cr_vtype_agnostic

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

cp_vl_0

x

x

x

x

x

x

x

x

x
Instruction vluxseg8ei32.v vluxseg8ei64.v vloxei8.v vloxei16.v vloxei32.v vloxei64.v vloxseg2ei8.v vloxseg2ei16.v vloxseg2ei32.v

Type

VXVM

VXVM

VXVM

VXVM

VXVM

VXVM

VXVM

VXVM

VXVM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

lte24

lte24

x

x

x

x

lte30

lte30

lte30

cp_vs2

x

x

x

x

x

x

x

x

x

cp_vs2_edges

ls

ls

ls

ls

ls

ls

ls

ls

ls

cp_rs1

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

e32_emul1max

e64_emul1max

e8

e16

e32

e64

e8_emul4max

e16_emul4max

e32_emul4max

cr_vtype_agnostic

e32_emul1max

e64_emul1max

e8

e16

e32

e64

e8_emul4max

e16_emul4max

e32_emul4max

cp_vl_0

x

x

x

x

x

x

x

x

x
Instruction vloxseg2ei64.v vloxseg3ei8.v vloxseg3ei16.v vloxseg3ei32.v vloxseg3ei64.v vloxseg4ei8.v vloxseg4ei16.v vloxseg4ei32.v vloxseg4ei64.v

Type

VXVM

VXVM

VXVM

VXVM

VXVM

VXVM

VXVM

VXVM

VXVM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

lte30

lte29

lte29

lte29

lte29

lte28

lte28

lte28

lte28

cp_vs2

x

x

x

x

x

x

x

x

x

cp_vs2_edges

ls

ls

ls

ls

ls

ls

ls

ls

ls

cp_rs1

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

e64_emul4max

e8_emul2max

e16_emul2max

e32_emul2max

e64_emul2max

e8_emul2max

e16_emul2max

e32_emul2max

e64_emul2max

cr_vtype_agnostic

e64_emul4max

e8_emul2max

e16_emul2max

e32_emul2max

e64_emul2max

e8_emul2max

e16_emul2max

e32_emul2max

e64_emul2max

cp_vl_0

x

x

x

x

x

x

x

x

x
Instruction vloxseg5ei8.v vloxseg5ei16.v vloxseg5ei32.v vloxseg5ei64.v vloxseg6ei8.v vloxseg6ei16.v vloxseg6ei32.v vloxseg6ei64.v vloxseg7ei8.v

Type

VXVM

VXVM

VXVM

VXVM

VXVM

VXVM

VXVM

VXVM

VXVM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

lte27

lte27

lte27

lte27

lte26

lte26

lte26

lte26

lte25

cp_vs2

x

x

x

x

x

x

x

x

x

cp_vs2_edges

ls

ls

ls

ls

ls

ls

ls

ls

ls

cp_rs1

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

cr_vtype_agnostic

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

cp_vl_0

x

x

x

x

x

x

x

x

x
Instruction vloxseg7ei16.v vloxseg7ei32.v vloxseg7ei64.v vloxseg8ei8.v vloxseg8ei16.v vloxseg8ei32.v vloxseg8ei64.v vse8.v vse16.v

Type

VXVM

VXVM

VXVM

VXVM

VXVM

VXVM

VXVM

VSXM

VSXM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

lte25

lte25

lte25

lte24

lte24

lte24

lte24

cp_vs3

x

x

cp_vs2

x

x

x

x

x

x

x

cp_vs2_edges

ls

ls

ls

ls

ls

ls

ls

cp_rs1

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8

e16

cr_vtype_agnostic

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8

e16

cp_vl_0

x

x

x

x

x

x

x

x

x
Instruction vse32.v vse64.v vsseg2e8.v vsseg2e16.v vsseg2e32.v vsseg2e64.v vsseg3e8.v vsseg3e16.v vsseg3e32.v

Type

VSXM

VSXM

VSXM

VSXM

VSXM

VSXM

VSXM

VSXM

VSXM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vs3

x

x

lte30

lte30

lte30

lte30

lte29

lte29

lte29

cp_rs1

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

e32

e64

e8_emul4max

e16_emul4max

e32_emul4max

e64_emul4max

e8_emul2max

e16_emul2max

e32_emul2max

cr_vtype_agnostic

e32

e64

e8_emul4max

e16_emul4max

e32_emul4max

e64_emul4max

e8_emul2max

e16_emul2max

e32_emul2max

cp_vl_0

x

x

x

x

x

x

x

x

x
Instruction vsseg3e64.v vsseg4e8.v vsseg4e16.v vsseg4e32.v vsseg4e64.v vsseg5e8.v vsseg5e16.v vsseg5e32.v vsseg5e64.v

Type

VSXM

VSXM

VSXM

VSXM

VSXM

VSXM

VSXM

VSXM

VSXM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vs3

lte29

lte28

lte28

lte28

lte28

lte27

lte27

lte27

lte27

cp_rs1

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

e64_emul2max

e8_emul2max

e16_emul2max

e32_emul2max

e64_emul2max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

cr_vtype_agnostic

e64_emul2max

e8_emul2max

e16_emul2max

e32_emul2max

e64_emul2max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

cp_vl_0

x

x

x

x

x

x

x

x

x
Instruction vsseg6e8.v vsseg6e16.v vsseg6e32.v vsseg6e64.v vsseg7e8.v vsseg7e16.v vsseg7e32.v vsseg7e64.v vsseg8e8.v

Type

VSXM

VSXM

VSXM

VSXM

VSXM

VSXM

VSXM

VSXM

VSXM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vs3

lte26

lte26

lte26

lte26

lte25

lte25

lte25

lte25

lte24

cp_rs1

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

cr_vtype_agnostic

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

cp_vl_0

x

x

x

x

x

x

x

x

x
Instruction vsseg8e16.v vsseg8e32.v vsseg8e64.v vsse8.v vsse16.v vsse32.v vsse64.v vssseg2e8.v vssseg2e16.v

Type

VSXM

VSXM

VSXM

VSXXM

VSXXM

VSXXM

VSXXM

VSXXM

VSXXM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vs3

lte24

lte24

lte24

x

x

x

x

lte30

lte30

cp_rs1

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

cp_rs2

x

x

x

x

x

x

cp_rs2_edges

ls_e8

ls_e16

ls_e32

ls_e64

ls_e8

ls_e16

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

e16_emul1max

e32_emul1max

e64_emul1max

e8

e16

e32

e64

e8_emul4max

e16_emul4max

cr_vtype_agnostic

e16_emul1max

e32_emul1max

e64_emul1max

e8

e16

e32

e64

e8_emul4max

e16_emul4max

cp_vl_0

x

x

x

x

x

x

x

x

x
Instruction vssseg2e32.v vssseg2e64.v vssseg3e8.v vssseg3e16.v vssseg3e32.v vssseg3e64.v vssseg4e8.v vssseg4e16.v vssseg4e32.v

Type

VSXXM

VSXXM

VSXXM

VSXXM

VSXXM

VSXXM

VSXXM

VSXXM

VSXXM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vs3

lte30

lte30

lte29

lte29

lte29

lte29

lte28

lte28

lte28

cp_rs1

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

cp_rs2

x

x

x

x

x

x

x

x

x

cp_rs2_edges

ls_e32

ls_e64

ls_e8

ls_e16

ls_e32

ls_e64

ls_e8

ls_e16

ls_e32

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

e32_emul4max

e64_emul4max

e8_emul2max

e16_emul2max

e32_emul2max

e64_emul2max

e8_emul2max

e16_emul2max

e32_emul2max

cr_vtype_agnostic

e32_emul4max

e64_emul4max

e8_emul2max

e16_emul2max

e32_emul2max

e64_emul2max

e8_emul2max

e16_emul2max

e32_emul2max

cp_vl_0

x

x

x

x

x

x

x

x

x
Instruction vssseg4e64.v vssseg5e8.v vssseg5e16.v vssseg5e32.v vssseg5e64.v vssseg6e8.v vssseg6e16.v vssseg6e32.v vssseg6e64.v

Type

VSXXM

VSXXM

VSXXM

VSXXM

VSXXM

VSXXM

VSXXM

VSXXM

VSXXM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vs3

lte28

lte27

lte27

lte27

lte27

lte26

lte26

lte26

lte26

cp_rs1

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

cp_rs2

x

x

x

x

x

x

x

x

x

cp_rs2_edges

ls_e64

ls_e8

ls_e16

ls_e32

ls_e64

ls_e8

ls_e16

ls_e32

ls_e64

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

e64_emul2max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

cr_vtype_agnostic

e64_emul2max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

cp_vl_0

x

x

x

x

x

x

x

x

x
Instruction vssseg7e8.v vssseg7e16.v vssseg7e32.v vssseg7e64.v vssseg8e8.v vssseg8e16.v vssseg8e32.v vssseg8e64.v vsuxei8.v

Type

VSXXM

VSXXM

VSXXM

VSXXM

VSXXM

VSXXM

VSXXM

VSXXM

VSXVM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vs3

lte25

lte25

lte25

lte25

lte24

lte24

lte24

lte24

x

cp_vs2

x

cp_vs2_edges

ls

cmp_vs3_vs2

x

cp_rs1

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

cp_rs2

x

x

x

x

x

x

x

x

cp_rs2_edges

ls_e8

ls_e16

ls_e32

ls_e64

ls_e8

ls_e16

ls_e32

ls_e64

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8

cr_vtype_agnostic

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8

cp_vl_0

x

x

x

x

x

x

x

x

x
Instruction vsuxei16.v vsuxei32.v vsuxei64.v vsuxseg2ei8.v vsuxseg2ei16.v vsuxseg2ei32.v vsuxseg2ei64.v vsuxseg3ei8.v vsuxseg3ei16.v

Type

VSXVM

VSXVM

VSXVM

VSXVM

VSXVM

VSXVM

VSXVM

VSXVM

VSXVM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vs3

x

x

x

lte30

lte30

lte30

lte30

lte29

lte29

cp_vs2

x

x

x

x

x

x

x

x

x

cp_vs2_edges

ls

ls

ls

ls

ls

ls

ls

ls

ls

cmp_vs3_vs2

x

x

x

lte30

lte30

lte30

lte30

lte29

lte29

cp_rs1

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

e16

e32

e64

e8_emul4max

e16_emul4max

e32_emul4max

e64_emul4max

e8_emul2max

e16_emul2max

cr_vtype_agnostic

e16

e32

e64

e8_emul4max

e16_emul4max

e32_emul4max

e64_emul4max

e8_emul2max

e16_emul2max

cp_vl_0

x

x

x

x

x

x

x

x

x
Instruction vsuxseg3ei32.v vsuxseg3ei64.v vsuxseg4ei8.v vsuxseg4ei16.v vsuxseg4ei32.v vsuxseg4ei64.v vsuxseg5ei8.v vsuxseg5ei16.v vsuxseg5ei32.v

Type

VSXVM

VSXVM

VSXVM

VSXVM

VSXVM

VSXVM

VSXVM

VSXVM

VSXVM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vs3

lte29

lte29

lte28

lte28

lte28

lte28

lte27

lte27

lte27

cp_vs2

x

x

x

x

x

x

x

x

x

cp_vs2_edges

ls

ls

ls

ls

ls

ls

ls

ls

ls

cmp_vs3_vs2

lte29

lte29

lte28

lte28

lte28

lte28

lte27

lte27

lte27

cp_rs1

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

e32_emul2max

e64_emul2max

e8_emul2max

e16_emul2max

e32_emul2max

e64_emul2max

e8_emul1max

e16_emul1max

e32_emul1max

cr_vtype_agnostic

e32_emul2max

e64_emul2max

e8_emul2max

e16_emul2max

e32_emul2max

e64_emul2max

e8_emul1max

e16_emul1max

e32_emul1max

cp_vl_0

x

x

x

x

x

x

x

x

x
Instruction vsuxseg5ei64.v vsuxseg6ei8.v vsuxseg6ei16.v vsuxseg6ei32.v vsuxseg6ei64.v vsuxseg7ei8.v vsuxseg7ei16.v vsuxseg7ei32.v vsuxseg7ei64.v

Type

VSXVM

VSXVM

VSXVM

VSXVM

VSXVM

VSXVM

VSXVM

VSXVM

VSXVM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vs3

lte27

lte26

lte26

lte26

lte26

lte25

lte25

lte25

lte25

cp_vs2

x

x

x

x

x

x

x

x

x

cp_vs2_edges

ls

ls

ls

ls

ls

ls

ls

ls

ls

cmp_vs3_vs2

lte27

lte26

lte26

lte26

lte26

lte25

lte25

lte25

lte25

cp_rs1

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

cr_vtype_agnostic

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

cp_vl_0

x

x

x

x

x

x

x

x

x
Instruction vsuxseg8ei8.v vsuxseg8ei16.v vsuxseg8ei32.v vsuxseg8ei64.v vsoxei8.v vsoxei16.v vsoxei32.v vsoxei64.v vsoxseg2ei8.v

Type

VSXVM

VSXVM

VSXVM

VSXVM

VSXVM

VSXVM

VSXVM

VSXVM

VSXVM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vs3

lte24

lte24

lte24

lte24

x

x

x

x

lte30

cp_vs2

x

x

x

x

x

x

x

x

x

cp_vs2_edges

ls

ls

ls

ls

ls

ls

ls

ls

ls

cmp_vs3_vs2

lte24

lte24

lte24

lte24

x

x

x

x

lte30

cp_rs1

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8

e16

e32

e64

e8_emul4max

cr_vtype_agnostic

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8

e16

e32

e64

e8_emul4max

cp_vl_0

x

x

x

x

x

x

x

x

x
Instruction vsoxseg2ei16.v vsoxseg2ei32.v vsoxseg2ei64.v vsoxseg3ei8.v vsoxseg3ei16.v vsoxseg3ei32.v vsoxseg3ei64.v vsoxseg4ei8.v vsoxseg4ei16.v

Type

VSXVM

VSXVM

VSXVM

VSXVM

VSXVM

VSXVM

VSXVM

VSXVM

VSXVM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vs3

lte30

lte30

lte30

lte29

lte29

lte29

lte29

lte28

lte28

cp_vs2

x

x

x

x

x

x

x

x

x

cp_vs2_edges

ls

ls

ls

ls

ls

ls

ls

ls

ls

cmp_vs3_vs2

lte30

lte30

lte30

lte29

lte29

lte29

lte29

lte28

lte28

cp_rs1

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

e16_emul4max

e32_emul4max

e64_emul4max

e8_emul2max

e16_emul2max

e32_emul2max

e64_emul2max

e8_emul2max

e16_emul2max

cr_vtype_agnostic

e16_emul4max

e32_emul4max

e64_emul4max

e8_emul2max

e16_emul2max

e32_emul2max

e64_emul2max

e8_emul2max

e16_emul2max

cp_vl_0

x

x

x

x

x

x

x

x

x
Instruction vsoxseg4ei32.v vsoxseg4ei64.v vsoxseg5ei8.v vsoxseg5ei16.v vsoxseg5ei32.v vsoxseg5ei64.v vsoxseg6ei8.v vsoxseg6ei16.v vsoxseg6ei32.v

Type

VSXVM

VSXVM

VSXVM

VSXVM

VSXVM

VSXVM

VSXVM

VSXVM

VSXVM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vs3

lte28

lte28

lte27

lte27

lte27

lte27

lte26

lte26

lte26

cp_vs2

x

x

x

x

x

x

x

x

x

cp_vs2_edges

ls

ls

ls

ls

ls

ls

ls

ls

ls

cmp_vs3_vs2

lte28

lte28

lte27

lte27

lte27

lte27

lte26

lte26

lte26

cp_rs1

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

e32_emul2max

e64_emul2max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

cr_vtype_agnostic

e32_emul2max

e64_emul2max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

cp_vl_0

x

x

x

x

x

x

x

x

x
Instruction vsoxseg6ei64.v vsoxseg7ei8.v vsoxseg7ei16.v vsoxseg7ei32.v vsoxseg7ei64.v vsoxseg8ei8.v vsoxseg8ei16.v vsoxseg8ei32.v vsoxseg8ei64.v

Type

VSXVM

VSXVM

VSXVM

VSXVM

VSXVM

VSXVM

VSXVM

VSXVM

VSXVM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vs3

lte26

lte25

lte25

lte25

lte25

lte24

lte24

lte24

lte24

cp_vs2

x

x

x

x

x

x

x

x

x

cp_vs2_edges

ls

ls

ls

ls

ls

ls

ls

ls

ls

cmp_vs3_vs2

lte26

lte25

lte25

lte25

lte25

lte24

lte24

lte24

lte24

cp_rs1

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

cr_vtype_agnostic

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

cp_vl_0

x

x

x

x

x

x

x

x

x
Instruction vl1re8.v vl2re8.v vl4re8.v vl8re8.v vl1re16.v vl2re16.v vl4re16.v vl8re16.v vl1re32.v

Type

VX

VX

VX

VX

VX

VX

VX

VX

VX

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

x

emul2

emul4

emul8

x

emul2

emul4

emul8

x

cp_rs1

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

cr_vl_lmul

x

lmul4max

lmul2max

lmul1max

x

lmul4max

lmul2max

lmul1max

x

cr_vtype_agnostic

nomask

lmul4max_nomask

lmul2max_nomask

lmul1max_nomask

nomask

lmul4max_nomask

lmul2max_nomask

lmul1max_nomask

nomask

cp_vl_0

x

x

x

x

x

x

x

x

x
Instruction vl2re32.v vl4re32.v vl8re32.v vl1re64.v vl2re64.v vl4re64.v vl8re64.v vs1r.v vs2r.v

Type

VX

VX

VX

VX

VX

VX

VX

VSX

VSX

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW8

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

emul2

emul4

emul8

x

emul2

emul4

emul8

cp_vs3

x

emul2

cp_rs1

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

cr_vl_lmul

lmul4max

lmul2max

lmul1max

x

lmul4max

lmul2max

lmul1max

x

x

cr_vtype_agnostic

lmul4max_nomask

lmul2max_nomask

lmul1max_nomask

nomask

lmul4max_nomask

lmul2max_nomask

lmul1max_nomask

nomask

nomask

cp_vl_0

x

x

x

x

x

x

x

x

x
Instruction vs4r.v vs8r.v vsm.v vlm.v

Type

VSX

VSX

VSX

VX

RV32

x

x

x

x

RV64

x

x

x

x

EFFEW8

x

x

x

x

EFFEW16

x

x

x

x

EFFEW32

x

x

x

x

EFFEW64

x

x

x

x

cp_asm_count

x

x

x

x

cp_vd

x

cp_vs3

emul4

emul8

x

cp_rs1

nx0

nx0

nx0

nx0

cr_vl_lmul

x

x

x

x

cr_vtype_agnostic

nomask

nomask

nomask

nomask

cp_vl_0

x

x

x

x

A.11.6. Vf

Table 110. Vf Instruction Coverpoints
Instruction vfadd.vv vfadd.vf vfwadd.vv vfwadd.vf vfwadd.wv vfwadd.wf vfsub.vv vfsub.vf vfwsub.vv

Type

VVVM

VVFM

VVVM

VVFM

VVVM

VVFM

VVVM

VVFM

VVVM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

x

x

emul2

emul2

emul2

emul2

x

x

emul2

cp_vs2

x

x

x

x

emul2

emul2

x

x

x

cp_vs1

x

x

x

x

x

cp_fs1

x

x

x

x

cmp_vd_vs2

x

x

emul2

emul2

x

x

cmp_vd_vs1

x

x

cmp_vs1_vs2

x

x

x

x

cmp_vd_vs1_vs2

x

x

cp_vs2_edges

f

f

f

f

f_emul2

f_emul2

f

f

f

cp_vs1_edges

f

f

f

f

f

cr_vs2_vs1_edges

f

f

fwv

f

f

cp_fs1_edges

v

v

v

v

cr_vs2_fs1_edges

x

x

wf

x

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

x

x

lmul4max

lmul4max

lmul4max

lmul4max

x

x

lmul4max

cr_vtype_agnostic

x

x

lmul4max

lmul4max

lmul4max

lmul4max

x

x

lmul4max

cp_vl_0

x

x

x

x

x

x

x

x

x

cp_csr_fflags

von

von

vn

vn

von

von

von

von

vn

cp_csr_frm

v

v

v

v

v

v

v

v

v
Instruction vfwsub.vf vfwsub.wv vfwsub.wf vfrsub.vf vfmul.vv vfmul.vf vfwmul.vv vfwmul.vf vfdiv.vv

Type

VVFM

VVVM

VVFM

VVFM

VVVM

VVFM

VVVM

VVFM

VVVM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

emul2

emul2

emul2

x

x

x

emul2

emul2

x

cp_vs2

x

emul2

emul2

x

x

x

x

x

x

cp_vs1

x

x

x

x

cp_fs1

x

x

x

x

x

cmp_vd_vs2

emul2

emul2

x

x

x

x

cmp_vd_vs1

x

x

cmp_vs1_vs2

x

x

x

cmp_vd_vs1_vs2

x

x

cp_vs2_edges

f

f_emul2

f_emul2

f

f

f

f

f

f

cp_vs1_edges

f

f

f

f

cr_vs2_vs1_edges

fwv

f

f

f

cp_fs1_edges

v

v

v

v

v

cr_vs2_fs1_edges

x

wf

x

x

x

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

lmul4max

lmul4max

lmul4max

x

x

x

lmul4max

lmul4max

x

cr_vtype_agnostic

lmul4max

lmul4max

lmul4max

x

x

x

lmul4max

lmul4max

x

cp_vl_0

x

x

x

x

x

x

x

x

x

cp_csr_fflags

vn

von

von

von

voun

voun

vun

vun

vdoun

cp_csr_frm

v

v

v

v

v

v

v

v

v
Instruction vfdiv.vf vfrdiv.vf vfmacc.vv vfmacc.vf vfnmacc.vv vfnmacc.vf vfmsac.vv vfmsac.vf vfnmsac.vv

Type

VVFM

VVFM

VVVMR

VFVM

VVVMR

VFVM

VVVMR

VFVM

VVVMR

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

x

x

x

x

x

x

x

x

x

cp_vs2

x

x

x

x

x

x

x

x

x

cp_vs1

x

x

x

x

cp_fs1

x

x

x

x

x

cmp_vd_vs2

x

x

x

x

x

x

x

x

x

cmp_vd_vs1

x

x

x

x

cmp_vs1_vs2

x

x

x

x

cmp_vd_vs1_vs2

x

x

x

x

cp_vs2_edges

f

f

f

f

f

f

f

f

f

cp_vs1_edges

f

f

f

f

cr_vs2_vs1_edges

f

f

f

f

cp_fs1_edges

v

v

v

v

v

cr_vs2_fs1_edges

x

x

x

x

x

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

x

x

x

x

x

x

x

x

x

cr_vtype_agnostic

x

x

x

x

x

x

x

x

x

cp_vl_0

x

x

x

x

x

x

x

x

x

cp_csr_fflags

vdoun

vdoun

voun

voun

voun

voun

voun

voun

voun

cp_csr_frm

v

v

v

v

v

v

v

v

v
Instruction vfnmsac.vf vfmadd.vv vfmadd.vf vfnmadd.vv vfnmadd.vf vfmsub.vv vfmsub.vf vfnmsub.vv vfnmsub.vf

Type

VFVM

VVVMR

VFVM

VVVMR

VFVM

VVVMR

VFVM

VVVMR

VFVM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

x

x

x

x

x

x

x

x

x

cp_vs2

x

x

x

x

x

x

x

x

x

cp_vs1

x

x

x

x

cp_fs1

x

x

x

x

x

cmp_vd_vs2

x

x

x

x

x

x

x

x

x

cmp_vd_vs1

x

x

x

x

cmp_vs1_vs2

x

x

x

x

cmp_vd_vs1_vs2

x

x

x

x

cp_vs2_edges

f

f

f

f

f

f

f

f

f

cp_vs1_edges

f

f

f

f

cr_vs2_vs1_edges

f

f

f

f

cp_fs1_edges

v

v

v

v

v

cr_vs2_fs1_edges

x

x

x

x

x

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

x

x

x

x

x

x

x

x

x

cr_vtype_agnostic

x

x

x

x

x

x

x

x

x

cp_vl_0

x

x

x

x

x

x

x

x

x

cp_csr_fflags

voun

voun

voun

voun

voun

voun

voun

voun

voun

cp_csr_frm

v

v

v

v

v

v

v

v

v
Instruction vfwmacc.vv vfwmacc.vf vfwnmacc.vv vfwnmacc.vf vfwmsac.vv vfwmsac.vf vfwnmsac.vv vfwnmsac.vf vfsqrt.v

Type

VVVMR

VFVM

VVVMR

VFVM

VVVMR

VFVM

VVVMR

VFVM

VVM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

emul2

emul2

emul2

emul2

emul2

emul2

emul2

emul2

x

cp_vs2

x

x

x

x

x

x

x

x

x

cp_vs1

x

x

x

x

cp_fs1

x

x

x

x

cmp_vd_vs2

x

cmp_vs1_vs2

x

x

x

x

cp_vs2_edges

f

f

f

f

f

f

f

f

f

cp_vs1_edges

f

f

f

f

cr_vs2_vs1_edges

f

f

f

f

cp_fs1_edges

v

v

v

v

cr_vs2_fs1_edges

x

x

x

x

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

lmul4max

lmul4max

lmul4max

lmul4max

lmul4max

lmul4max

lmul4max

lmul4max

x

cr_vtype_agnostic

lmul4max

lmul4max

lmul4max

lmul4max

lmul4max

lmul4max

lmul4max

lmul4max

x

cp_vl_0

x

x

x

x

x

x

x

x

x

cp_csr_fflags

vun

vun

vun

vun

vun

vun

vun

vun

vn

cp_csr_frm

v

v

v

v

v

v

v

v

v
Instruction vfrsqrt7.v vfrec7.v vfmin.vv vfmin.vf vfmax.vv vfmax.vf vfsgnj.vv vfsgnj.vf vfsgnjn.vv

Type

VVM

VVM

VVVM

VVFM

VVVM

VVFM

VVVM

VVFM

VVVM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

x

x

x

x

x

x

x

x

x

cp_vs2

x

x

x

x

x

x

x

x

x

cp_vs1

x

x

x

x

cp_fs1

x

x

x

cmp_vd_vs2

x

x

x

x

x

x

x

x

x

cmp_vd_vs1

x

x

x

x

cmp_vs1_vs2

x

x

x

x

cmp_vd_vs1_vs2

x

x

x

x

cp_vs2_edges

f

f

f

f

f

f

f

f

f

cp_vs1_edges

f

f

f

f

cr_vs2_vs1_edges

f

f

f

f

cp_fs1_edges

v

v

v

cr_vs2_fs1_edges

x

x

x

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

x

x

x

x

x

x

x

x

x

cr_vtype_agnostic

x

x

x

x

x

x

x

x

x

cp_vl_0

x

x

x

x

x

x

x

x

x

cp_csr_fflags

vd

vdon

v

v

v

v

cp_csr_frm

v

v
Instruction vfsgnjn.vf vfsgnjx.vv vfsgnjx.vf vfredosum.vs vfwredosum.vs vfredusum.vs vfwredusum.vs vfredmax.vs vfredmin.vs

Type

VVFM

VVVM

VVFM

VVVM

VVVM

VVVM

VVVM

VVVM

VVVM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

x

x

x

x

emul2

x

emul2

x

x

cp_vs2

x

x

x

x

x

x

x

x

x

cp_vs1

x

x

emul2

x

emul2

x

x

cp_fs1

x

x

cmp_vd_vs2

x

x

x

x

x

x

x

cmp_vd_vs1

x

x

emul2

x

emul2

x

x

cmp_vs1_vs2

x

x

x

x

x

cmp_vd_vs1_vs2

x

x

x

x

x

cp_vs2_edges

f

f

f

f

f

f

f

f

f

cp_vs1_edges

f

f

f_emul2

f

f_emul2

f

f

cr_vs2_vs1_edges

f

f

fwred

f

fwred

f

f

cp_fs1_edges

v

v

cr_vs2_fs1_edges

x

x

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

x

x

x

x

lmul4max

x

lmul4max

x

x

cr_vtype_agnostic

x

x

x

x

lmul4max

x

lmul4max

x

x

cp_vl_0

x

x

x

x

x

x

x

x

x

cp_csr_fflags

von

vn

von

vn

v

v

cp_csr_frm

v

v

v

v
Instruction vmfeq.vv vmfeq.vf vmfne.vv vmfne.vf vmflt.vv vmflt.vf vmfle.vv vmfle.vf vmfgt.vf

Type

VVVM

VVFM

VVVM

VVFM

VVVM

VVFM

VVVM

VVFM

VVFM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

x

x

x

x

x

x

x

x

x

cp_vs2

x

x

x

x

x

x

x

x

x

cp_vs1

x

x

x

x

cp_fs1

x

x

x

x

x

cmp_vs1_vs2

x

x

x

x

cp_vs2_edges

f

f

f

f

f

f

f

f

f

cp_vs1_edges

f

f

f

f

cr_vs2_vs1_edges

f

f

f

f

cp_fs1_edges

v

v

v

v

v

cr_vs2_fs1_edges

x

x

x

x

x

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

x

x

x

x

x

x

x

x

x

cr_vtype_agnostic

x

x

x

x

x

x

x

x

x

cp_vl_0

x

x

x

x

x

x

x

x

x

cp_csr_fflags

v

v

v

v

v

v

v

v

v
Instruction vmfge.vf vfmerge.vfm vfmv.v.f vfmv.f.s vfmv.s.f vfslide1up.vf vfslide1down.vf vfcvt.xu.f.v vfwcvt.xu.f.v

Type

VVFM

VVFM

VF

FV

VF

VVFM

VVFM

VVM

VVM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

x

nv0

x

x

x

x

x

emul2

cp_fd

x

cp_vs2

x

nv0

x

x

x

x

x

cp_fs1

x

x

x

x

x

x

cmp_vd_vs2

nv0

x

x

cp_vs2_edges

f

f

f

f

f

f

f

cp_fs1_edges

v

v

v

v

v

v

cr_vs2_fs1_edges

x

x

x

x

cp_masking_edges

x

x

x

x

x

x

cr_vl_lmul

x

x

x

x

x

x

x

x

lmul4max

cr_vtype_agnostic

x

x

nomask

nomask

nomask

x

x

x

lmul4max

cp_vl_0

x

x

x

x

x

x

x

x

x

cp_csr_fflags

v

vn

vn

cp_csr_frm

v

v
Instruction vfncvt.xu.f.w vfcvt.x.f.v vfwcvt.x.f.v vfncvt.x.f.w vfcvt.rtz.xu.f.v vfwcvt.rtz.xu.f.v vfncvt.rtz.xu.f.w vfcvt.rtz.x.f.v vfwcvt.rtz.x.f.v

Type

VVM

VVM

VVM

VVM

VVM

VVM

VVM

VVM

VVM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

x

EFFEW64

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

x

x

emul2

x

x

emul2

x

x

emul2

cp_vs2

emul2

x

x

emul2

x

x

emul2

x

x

cmp_vd_vs2

x

x

x

cp_vs2_edges

f_emul2

f

f

f_emul2

f

f

f_emul2

f

f

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

lmul4max

x

lmul4max

lmul4max

x

lmul4max

lmul4max

x

lmul4max

cr_vtype_agnostic

lmul4max

x

lmul4max

lmul4max

x

lmul4max

lmul4max

x

lmul4max

cp_vl_0

x

x

x

x

x

x

x

x

x

cp_csr_fflags

vn

vn

vn

vn

vn

vn

vn

vn

vn

cp_csr_frm

v

v

v

v
Instruction vfncvt.rtz.x.f.w vfcvt.f.xu.v vfwcvt.f.xu.v vfncvt.f.xu.w vfcvt.f.x.v vfwcvt.f.x.v vfncvt.f.x.w vfwcvt.f.f.v vfncvt.f.f.w

Type

VVM

VVM

VVM

VVM

VVM

VVM

VVM

VVM

VVM

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

EFFEW16

x

x

x

x

x

x

x

x

EFFEW32

x

x

x

x

x

x

x

x

EFFEW64

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_vd

x

x

emul2

x

x

emul2

x

emul2

x

cp_vs2

emul2

x

x

emul2

x

x

emul2

x

emul2

cmp_vd_vs2

x

x

cp_vs2_edges

f_emul2

f

f

f_emul2

f

f

f_emul2

f

f_emul2

cp_masking_edges

x

x

x

x

x

x

x

x

x

cr_vl_lmul

lmul4max

x

lmul4max

lmul4max

x

lmul4max

lmul4max

lmul4max

lmul4max

cr_vtype_agnostic

lmul4max

x

lmul4max

lmul4max

x

lmul4max

lmul4max

lmul4max

lmul4max

cp_vl_0

x

x

x

x

x

x

x

x

x

cp_csr_fflags

vn

n

n

n

n

v

voun

cp_csr_frm

v

v

v

v

v
Instruction vfncvt.rod.f.f.w vfclass.v

Type

VVM

VVM

RV32

x

x

RV64

x

x

EFFEW16

x

x

EFFEW32

x

x

EFFEW64

x

cp_asm_count

x

x

cp_vd

x

x

cp_vs2

emul2

x

cmp_vd_vs2

x

cp_vs2_edges

f_emul2

f

cp_masking_edges

x

x

cr_vl_lmul

lmul4max

x

cr_vtype_agnostic

lmul4max

x

cp_vl_0

x

x

cp_csr_fflags

voun
vfredusum.vs is difficult to test because the results depend on the ordering. It is not presently tested for multi-element vectors.

A.11.7. Zvfh Vector Half-Precision Floating-Point Extension

Half-precision vector floating-point is part of the Zvfh and Zvfhmin extensions, not the base V extension. Nevertheless, Zvfh tests are in the same directory structure as V, under Vf16. Zvfh uses Vf16 Table 110 to exercise all floating-point instructions with SEW=16.

A.11.8. Zvfhmin Half-Precision Conversions

Zvfhmin only exercises the widening and narrowing conversions: vfwcvt.f.f.v and vfncvt.f.f.w.

Table 111. Zvfhmin Instruction Coverpoints
Instruction vfwcvt.f.f.v vfncvt.f.f.w

Type

VVM

VVM

RV32

x

x

RV64

x

x

EFFEW16

x

EFFEW32

x

cp_asm_count

x

x

cp_vd

emul2

x

cp_vs2

x

emul2

cp_vs2_edges

f

f_emul2

cp_masking_edges

x

x

cr_vl_lmul

lmul4max

lmul4max

cr_vtype_agnostic

lmul4max

lmul4max

cp_vl_0

x

x

cp_csr_fflags

v

voun

cp_csr_frm

v
Table 112. Zvfhmin Normative Rules
Normative Rule Rule Text Coverpoints

UDB Parameters: None.

A.11.9. ZfaZvfh Half-Precision Load Immediate

When Zfa and Zvfh are both implemented, RISC-V provides a fli.h instruction (Table 113) even if full Zfh is not supported.

Table 113. ZfaZvfh Instruction Coverpoints
Instruction fli.h

Type

FLI

RV32

x

RV64

x

cp_asm_count

x

cp_rs1

fli

cp_fd

x

cp_NaNBox

S_H
Table 114. ZfaZvfh Normative Rules
Normative Rule Rule Text Coverpoints

fli-h_op

If the Zfh or Zvfh extension is implemented, FLI.H performs the analogous operation, but loads a half-precision floating-point value into register rd. Note that entry 1 (corresponding to the minimum positive normal value) has a numerically different value for half-precision. Furthermore, since 216 is not representable in half-precision floating-point, entry 29 in the table instead loads positive infinity—i.e., it is redundant with entry 30. FLI.H is encoded like FLI.S, but with fmt=H.

ZfaZvfh_fli_h_cg/{cp_rs1_fli, cp_fd, cp_NaNBox_S_H}

UDB Parameters: None.

A.11.10. Zvfbfmin BF16 Conversions

Table 115. Zvfbfmin Instruction Coverpoints
Instruction vfwcvtbf16.f.f.v vfncvtbf16.f.f.w

Type

VVM

VVM

RV32

x

x

RV64

x

x

EFFEW16

x

EFFEW32

x

cp_asm_count

x

x

cp_vd

emul2

x

cp_vs2

x

emul2

cp_vs2_edges

f

f_emul2

cp_masking_edges

x

x

cr_vl_lmul

lmul4max

lmul4max

cr_vtype_agnostic

lmul4max

lmul4max

cp_vl_0

x

x

cp_csr_fflags

v

voun

cp_csr_frm

v
Table 116. Zvfbfmin Normative Rules
Normative Rule Rule Text Coverpoints

vfwcvtbf16-f-f-v_op

Widening convert from BF16 to FP32. The conversion is exact.

Zvfbfmin_vfwcvtbf16_f_f_v_cg/{cp_vd_emul2, cp_vs2, cp_vs2_edges_f, cp_masking_edges, cr_vl_lmul_lmul4max, cr_vtype_agnostic_lmul4max, cp_vl_0, cp_csr_fflags_v}

vfncvtbf16-f-f-w_op

Narrowing convert from FP32 to BF16. Round according to the frm register.

Zvfbfmin_vfncvtbf16_f_f_w_cg/{cp_vd, cp_vs2_emul2, cp_vs2_edges_f_emul2, cp_masking_edges, cr_vl_lmul_lmul4max, cr_vtype_agnostic_lmul4max, cp_vl_0, cp_csr_fflags_voun, cp_csr_frm_v}

UDB Parameters: None.

A.11.11. Zvfbfwma BF16 MAC

Table 117. Zvfbfwma Instruction Coverpoints
Instruction vfwmaccbf16.vv vfwmaccbf16.vf

Type

VVVMR

VFVM

RV32

x

x

RV64

x

x

EFFEW16

x

x

cp_asm_count

x

x

cp_vd

emul2

emul2

cp_vs2

x

x

cp_vs1

x

cp_fs1

x

cmp_vs1_vs2

x

cp_vs2_edges

f

f

cp_vs1_edges

f

cr_vs2_vs1_edges

f

cp_fs1_edges

v

cr_vs2_fs1_edges

x

cp_masking_edges

x

x

cr_vl_lmul

lmul4max

lmul4max

cr_vtype_agnostic

lmul4max

lmul4max

cp_vl_0

x

x

cp_csr_fflags

vun

vun

cp_csr_frm

v

v
Table 118. Zvfbfwma Normative Rules
Normative Rule Rule Text Coverpoints

vfwmaccbf16_vf_op

This instruction performs a widening fused multiply-accumulate operation, where each pair of BF16 values are multiplied and their unrounded product is added to the corresponding FP32 accumulate value. The sum is rounded according to the frm register. The vector-scalar version is similar, but instead of reading elements from vs1, a scalar BF16 value is read from the FPU register rs1. All of the BF16 instructions in the extensions defined in this specification (i.e., Zfbfmin, Zvfbfmin, and Zvfbfwma) fully support subnormal numbers. That is, instructions are able to accept subnormal values as inputs and they can produce subnormal results.

vfwmaccbf16_vf_sew_rsv

SEW is any value other than 16

vfwmaccbf16_vv_op

This instruction performs a widening fused multiply-accumulate operation, where each pair of BF16 values are multiplied and their unrounded product is added to the corresponding FP32 accumulate value. The sum is rounded according to the frm register. In the vector-vector version, the BF16 elements are read from vs1 and vs2 and FP32 accumulate value is read from vd. The FP32 result is written to the destination register vd. All of the BF16 instructions in the extensions defined in this specification (i.e., Zfbfmin, Zvfbfmin, and Zvfbfwma) fully support subnormal numbers. That is, instructions are able to accept subnormal values as inputs and they can produce subnormal results.

vfwmaccbf16_vv_sew_rsv

SEW is any value other than 16

UDB Parameters: None.

A.12. Zvb* Vector Bit Manipulation Extension

Vector bit manipulation extensions include Zvbb and Zvbc.

A.12.1. Zvbb Vector Basic Bit Manipulation Extension

A.12.2. Zvbc Vector Caryless Multiplication Extension

A.13. Zvk* Vector Cryptography Extension

Zvbc Instruction Coverpoints

There are several Zvk* vector cryptography extensions.

A.13.1. Zvkb Vector Crypto Bit Manipulation Extension

A.13.2. Zvkg Vector Crypto Galois Field Extension

A.13.3. Zvkned Vector NIST Encryption and Decryption

A.13.4. Zvknh{a/b} Vector NIST Hashing

Zvkned Instruction Coverpoints

Section A.13.5 lists the vector hashing instructions. These apply to both Zknha and Zknhb.

A.13.5. Zvksed Vector ShangMi SM4 Block Cipher

A.13.6. Zvksh Vector ShangMi SM3 Hashing

A.14. Miscellaneous RV23 Unprivileged Extensions

A.14.1. Zacas Atomic Compare-and-Swap

Table 119. Zacas Instruction Coverpoints
Instruction amocas.w amocas.d amocas.d amocas.q

Type

A

A

AP

AP

RV32

x

x

RV64

x

x

x

cp_asm_count

x

x

x

x

cp_rs1

nx0

nx0

nx0

nx0

cp_rs2

x

x

pair

pair

cp_rd

x

x

pair

pair

cp_rs2_edges

x

x

x

x

cmp_rs1_rs2

nx0

nx0

nx0_pair

nx0_pair

cmp_rd_rs1

nx0

nx0

nx0_pair

nx0_pair

cmp_rd_rs2

x

x

pair

pair

cmp_rd_rs1_rs2

nx0

nx0

nx0_pair

nx0_pair

cp_align

word
Table 120. Zacas Normative Rules
Normative Rule Rule Text Coverpoints

Zacas_rv32_amocas-w_op

For RV32, AMOCAS.W atomically loads a 32-bit data value from address in rs1, compares the loaded value to the 32-bit value held in rd, and if the comparison is bitwise equal, then stores the 32-bit value held in rs2 to the original address in rs1. The value loaded from memory is placed into register rd.

Zacas_rv32_amocas-d_op

For RV32, AMOCAS.D atomically loads 64-bits of a data value from address in rs1, compares the loaded value to a 64-bit value held in a register pair consisting of rd and rd+1, and if the comparison is bitwise equal, then stores the 64-bit value held in the register pair rs2 and rs2+1 to the original address in rs1. The value loaded from memory is placed into the register pair rd and rd+1.

Zacas_rv32_amocas-d_frst_pair_entry_reg_even

The instruction requires the first register in the pair to be even numbered; encodings with odd numbered registers specified in rs2 and rd are reserved.

Zacas_rv32_amocas-d_rs2_frst_reg_x0

When the first register of a source register pair is x0, then both halves of the pair read as zero.

Zacas_rv32_amocas-d_rd_frst_reg_x0

When the first register of a destination register pair is x0, then the entire register result is discarded and neither destination register is written.

Zacas_rv64_amocas-w_op

For RV64, AMOCAS.W atomically loads a 32-bit data value from address in rs1, compares the loaded value to the lower 32 bits of the value held in rd, and if the comparison is bitwise equal, then stores the lower 32 bits of the value held in rs2 to the original address in rs1. The 32-bit value loaded from memory is sign-extended and is placed into register rd.

Zacas_rv64_amocas-d_op

For RV64, AMOCAS.D atomically loads 64-bits of a data value from address in rs1, compares the loaded value to a 64-bit value held in rd, and if the comparison is bitwise equal, then stores the 64-bit value held in rs2 to the original address in rs1. The value loaded from memory is placed into register rd.

Zacas_rv64_amocas-q_op

AMOCAS.Q (RV64 only) atomically loads 128-bits of a data value from address in rs1, compares the loaded value to a 128-bit value held in a register pair consisting of rd and rd+1, and if the comparison is bitwise equal, then stores the 128-bit value held in the register pair rs2 and rs2+1 to the original address in rs1. The value loaded from memory is placed into the register pair rd and rd+1.

Zacas_rv64_amocas-q_frst_pair_entry_reg_even

The instruction requires the first register in the pair to be even numbered; encodings with odd numbered registers specified in rs2 and rd are reserved.

Zacas_rv64_amocas-q_rs2_frst_reg_x0

When the first register of a source register pair is x0, then both halves of the pair read as zero.

Zacas_rv64_amocas-q_rd_frst_reg_x0

When the first register of a destination register pair is x0, then the entire register result is discarded and neither destination register is written.

Zacas_amocas_rs1_addr_alignment

AMOCAS.W/D/Q requires that the address held in rs1 be naturally aligned to the size of the operand (i.e., 16-byte aligned for quadwords, eight-byte aligned for doublewords, and four-byte aligned for words).

Zacas_amocas_mem_op_success_aq_rl

The memory operation performed by an AMOCAS.W/D/Q, when successful, has acquire semantics if aq bit is 1 and has release semantics if rl bit is 1.

Zacas_amocas_mem_op_fail_aq_rl

The memory operation performed by an AMOCAS.W/D/Q, when not successful, has acquire semantics if aq bit is 1 but does not have release semantics, regardless of rl.

Zacas_amocas_w_permission

An AMOCAS.W/D/Q instruction always requires write permissions.

UDB Parameters: None.

TODO: Add .d to RV32 and .q to RV64 in testplans directory when testgen is updated to handle register pairs.

A.14.2. Zabha Subword Atomics

Table 121. Zabha Instruction Coverpoints
Instruction amoadd.b amoadd.h amoand.b amoand.h amomax.b amomax.h amomaxu.b amomaxu.h amomin.b

Type

A

A

A

A

A

A

A

A

A

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_rs1

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

cp_rs2

x

x

x

x

x

x

x

x

x

cp_rd

x

x

x

x

x

x

x

x

x

cp_rs2_edges

x

x

x

x

x

x

x

x

x

cmp_rs1_rs2

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

cmp_rd_rs1

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

cmp_rd_rs2

x

x

x

x

x

x

x

x

x

cmp_rd_rs1_rs2

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

cp_align

byte

hword

byte

hword

byte

hword

byte

hword

byte
Instruction amomin.h amominu.b amominu.h amoor.b amoor.h amoswap.b amoswap.h amoxor.b amoxor.h

Type

A

A

A

A

A

A

A

A

A

RV32

x

x

x

x

x

x

x

x

x

RV64

x

x

x

x

x

x

x

x

x

cp_asm_count

x

x

x

x

x

x

x

x

x

cp_rs1

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

cp_rs2

x

x

x

x

x

x

x

x

x

cp_rd

x

x

x

x

x

x

x

x

x

cp_rs2_edges

x

x

x

x

x

x

x

x

x

cmp_rs1_rs2

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

cmp_rd_rs1

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

cmp_rd_rs2

x

x

x

x

x

x

x

x

x

cmp_rd_rs1_rs2

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

nx0

cp_align

hword

byte

hword

byte

hword

byte

hword

byte

hword
Table 122. Zabha Normative Rules
Normative Rule Rule Text Coverpoints

Zabha_rd_sign_extension

Byte and halfword AMOs always sign-extend the value placed in rd, and ignore the

{Zabha_amoswap_b_cg, Zabha_amoswap_h_cg}/cp_rs2_edges

Zabha_rs1_align_addr

Similar to the AMOs specified in the A extension, the Zabha extension mandates that the address contained in the rs1 register must be naturally aligned to the size of the operand.

Zabha_amoswap_b_cg/cp_align_byte, Zabha_amoswap_h_cg/cp_align_hword

UDB Parameters: None.

A.14.3. ZacasZabha Subword Atomic Compare-and-Swap

Table 123 summarizes the coverpoints applicable when both Zacas and Zabha are supported.

Table 123. ZacasZabha Instruction Coverpoints
Instruction amocas.h amocas.b

Type

A

A

RV32

x

x

RV64

x

x

cp_asm_count

x

x

cp_rs1

nx0

nx0

cp_rs2

x

x

cp_rd

x

x

cp_rs2_edges

x

x

cmp_rs1_rs2

nx0

nx0

cmp_rd_rs1

nx0

nx0

cmp_rd_rs2

x

x

cmp_rd_rs1_rs2

nx0

nx0

cp_align

hword

byte
Table 124. ZacasZabha Normative Rules
Normative Rule Rule Text Coverpoints

Zabha_amocas-BH_ignore_bits

The AMOCAS.[B|H] instructions similarly ignore the

{ZacasZabha_amocas_b_cg, ZacasZabha_amocas_h_cg}/cp_rs2_edges

UDB Parameters: None.

A.14.4. Zimop Maybe-Ops

Should write 0 to rd unless implemented.

A.14.5. Zcmop Compressed Maybe-Ops

Zimop Coverpoints

Should write 0 to rd unless implemented.

A.15. Miscellaneous Non-RV23 Unprivileged Extensions

A.15.1. Zfinx Float in Integer Regs

Zcmop Coverpoints

Zfinx replaces the F extension with a similar set of instructions that operate on x registers instead of f registers. Zdinx and Zhinx are similar.

A.15.2. Zdinx Double in Integer Regs

A.15.3. Zhinx Half in Integer Regs

A.15.4. Zhinxmin Half Converts in Integer Regs

A.15.5. Q Quad-Precision Floating-Point

A.15.6. ZfhQ Half-Quad Instructions

A.15.7. ZfhminQ Half-Quad Conversion Instructions

ZfhQ Coverpoints

Note that ZfhminQ is the same as ZfhQ

A.15.8. ZfaQ Additional Quad-Precision Floating-Point Instructions

A.15.9. ZfaZfhQ Additional Half-Quad Conversion Instructions

A.15.10. Zcmp Compressed Push/Pop

Table 125. Zcmp Normative Rules
Normative Rule Rule Text Coverpoints

Zcmp_bus_fault

Stores may also return imprecise faults from the bus. It is platform defined whether the core implementation waits for the bus responses before continuing to the final stage of the sequence, or handles errors responses after completing the PUSH instruction.

TODO

Zcmp_pop_sp_commit

The optional li a0, 0, stack pointer adjustment and optional ret must only be committed only when it is certain that the entire POP/POPRET instruction will commit.

TODO

Zcmp_push_sp_commit

The stack pointer adjustment must only be committed only when it is certain that the entire PUSH instruction will commit.

TODO

Zcmp_trap

Correct execution requires that sp refers to idempotent memory (also see ), because the core must be able to handle traps detected during the sequence. The entire PUSH/POP sequence is re-executed after returning from the trap handler, and multiple traps are possible during the sequence. If a trap occurs during the sequence then xEPC is updated with the PC of the instruction, xTVAL (if not read-only-zero) updated with the bad address if it was an access fault and xCAUSE updated with the type of trap.

TODO

UDB Parameters: None.

A.15.11. Zcmt Compressed Jump Tables

Table 126. Zcmt Normative Rules
Normative Rule Rule Text Coverpoints

cm-jalt_op

cm.jalt reads an entry from the jump vector table in memory and jumps to the address that was read, linking to ra.

TODO

cm-jt_op

cm.jt reads an entry from the jump vector table in memory and jumps to the address that was read.

TODO

cm-mva01s_op

moves r1s' into a0 and r2s' into a1.

TODO

cm-mva01s_sreg

The encoding uses sreg number specifiers instead of xreg number specifiers to save encoding space.

TODO

cm-mvsa01_op

moves a0 into r1s' and a1 into r2s'. r1s' and r2s' must be different.

TODO

cm-mvsa01_sreg

The encoding uses sreg number specifiers instead of xreg number specifiers to save encoding space.

TODO

cm-pop_op

This instruction pops (loads) the registers in reg_list from stack memory, and then adjusts the stack pointer by stack_adj.

TODO

cm-popret_op

pops (loads) the registers in reg_list from stack memory, adjusts the stack pointer by stack_adj and then returns to ra.

TODO

cm-popretz_op

pops (loads) the registers in reg_list from stack memory, adjusts the stack pointer by stack_adj, moves zero into a0 and then returns to ra.

TODO

cm-push_op

pushes (stores) the registers in reg_list to the memory below the stack pointer, and then creates the stack frame by decrementing the stack pointer by stack_adj, including any additional stack space requested by the value of spimm.

TODO

interrupts_allowed_in_pushpop

TODO

jvt_base_vm

jvt.base is a virtual address, whenever virtual memory is enabled.

TODO

jvt_en

TODO

jvt_mode_acc

jvt.mode is a WARL field, so can only be programmed to modes which are implemented.

TODO

jvt_op

If [Zcmt] is implemented then jvt must also be implemented, but can contain a read-only value. If jvt is writable, the set of values the register may hold can vary by implementation. The value in the BASE field must always be aligned on a 64-byte boundary. Note that the CSR contains only bits XLEN-1 through 6 of the address base. When computing jump-table accesses, the lower six bits of base are filled with zeroes to obtain an XLEN-bit jump-table base address jvt.base that is always aligned on a 64-byte boundary.

TODO

jvt_reg

The jvt register is an XLEN-bit WARL read/write register that holds the jump table configuration, consisting of the jump table base address (BASE) and the jump table mode (MODE).

Zcmt_endian

Table entries follow the current data endianness. This is different from normal instruction fetch which is always little-endian.

TODO

Zcmt_entry_sz

The base of the table is in the jvt CSR (see [csrs-jvt]), each table entry is XLEN bits.

TODO

Zcmt_fetch

For a table jump instruction, the table entry that the instruction selects is considered an extension of the instruction itself. Hence, the execution of a table jump instruction involves two instruction fetches, the first to read the instruction (cm.jt/cm.jalt) and the second to read from the jump vector table (JVT). Both instruction fetches are implicit reads, and both require execute permission; read permission is irrelevant. It is recommended that the second fetch be ignored for hardware triggers and breakpoints.

TODO

Zcmt_table

Table jump uses a 256-entry XLEN wide table in instruction memory to contain function addresses. The table must be a minimum of 64-byte aligned.

TODO

Zcmt_trap

If an exception occurs on either instruction fetch, xEPC is set to the PC of the table jump instruction, xCAUSE is set as expected for the type of fault and xTVAL (if not set to zero) contains the fetch address which caused the fault.

TODO

UDB Parameters: None.

A.15.12. Zilsd Load/Store Double

A.15.13. Zclsd Compressed Load/Store Double

A.16. E Base Embedded Extension

Zclsd Coverpoints

The E Base ISA is a variant of I with 16 general purpose registers. This test plan also includes tests restricted to these 16 registers for simple extensions most likely to be implemented on an embedded core.

All unprivileged tests for RV32 and RV64 can have E equivalents. They are distinguished in the tests directory by rv32i, rv64i, rv32e, and rv64e subdirectories. By default, the test generator only creates rv32e/rv64e tests for the following extensions because embedded cores are most likely to implement these extensions. However, embedded tests for more extensions can be generated by editing the E_EXTENSION_TESTS variable in the riscv-arch-test generators/testgen/src/testgen/testgen.py script.

  • E (base ISA)

  • M (multiply/divide)

  • Zmmul (multiply)

  • Zca (compressed)

  • Zcb (more compressed)

  • Zcmp (compressed push/pop)

  • Zcmt (compressed table jumps)

  • Zba (bitmanip address)

  • Zbb (bitmanip basic)

  • Zbs (bitmanip single-bit)

The normative rule specific to the E base ISA is given in Table 127. Each instruction also has normative rules inherited from its extension.

Table 127. E Normative Rules
Normative Rule Rule Text Coverpoints

diff-rv32e-rv32i

RV32E and RV64E use the same instruction-set encoding as RV32I and RV64I respectively, except that only registers x0-x15 are provided. All encodings specifying the other registers x16-x31 are reserved.

I_add_cg/{cp_rs1, cp_rs2, cp_rd, cmp_rd_rs1, cmp_rd_rs2, cmp_rs1_rs2, cmp_rd_rs1_rs2}, {SsstrictS_cg,SsstricM_cg}/{cp_upperreg}

UDB Parameters: None.

The E base ISA and other extensions based on it use the same coverpoints as the I base ISA. However, the register coverpoints such as cp_rd, cpr_rs1, cp_rs2, cmp_rd_rs1, etc. only exercise the 16 registers x0 through x15 when E is enabled. (See the get_gpr_reg function in framework/src/act/fcov/coverage/RISCV_instruction_base.svh, which is controlled by the COVER_E symbol).

Privileged tests are written using only x0-x15, so they work for both E and I base ISAs. One exception is that Ssstrict tests using the upper registers, which should be reserved and trap in E.

Appendix B: Privileged Test Plan

Privileged test plan spreadsheets are available. They need to be edited into a more standardized format. Each test plan spreadsheet contains multiple columns for the applicable configurations. For example, Sm applies to any configuration with machine mode, S applies to any configuration with supervisor mode, and SmF applies to any configuration with floating-point.

The privileged testplan is organized by major categories of behaviors or extensions in the following sections. Each of these categories has multiple coverage files with suffixes indicating the circumstances to which they apply. For example, InterruptsSm applies to any configuration with Zicsr and M-mode. InterruptsU applies to any configuration with Zicsr and U-mode. InterruptsS applies to any configuration with Zicsr and S-mode. S-mode implies the presence of U and M modes so all three coverage files apply to a system with S-mode. Moreover, InterruptsS includes tests that execute in U and M-mode, such as setting a bit in mideleg and then checking that the corresponding interrupt is delegated to S-mode when taken in U-mode, but not when taken in M-mode.

B.1. Priv

The privileged tests exercise CSRs that are mandatory in each privilege mode. They also test mandatory privileged instructions: ecall, ebreak, mret, and sret. The CSR read/write/set/clear instructions themselves are tested in the unprivileged Zicsr tests of Section A.10.1.

wfi is tested in Section B.3 and sfence.vma is tested in Section B.8.

Privileged tests do not test reserved or custom instructions or CSRs because their behavior is UNSPECIFIED. Reserved instructions and CSRs are tested in the Section B.6 Ssstrict tests, where they should throw an Illegal Instruction exception if not implemented.

B.1.1. Sm Machine-Mode CSRs and Instructions

These test CSRs and privileged instructions in machine mode.

Table 128. Sm Coverpoints

Google Sheet Testplan

TODO: Plan how to check WARL, WPRI, WLRL fields. It seems every CSR needs parameters, either to tell the reference model how they should behave (to generate expected values), or to tell the tests and coverpoints which values are legal to test.

Table 129. Sm Normative Rules
Normative Rule Rule Text Coverpoints

M_highest_priv_mode

machine-mode (M-mode), which is the highest privilege mode in a RISC-V hart.

Implicit

M_mode_at_reset

Sm_mcsr_cg/cp_mcsr_access runs right after booting and requires M-mode

M_access_all_lower_priv_CSRs

M-mode code can access all CSRs at lower privilege levels.

S_scsr_cg/cp_scsr_from_m, UF_ufcsr_cg/cp_ufcsr_from_m, UV_vucsr_cg/cp_vucsr_from_m, H_mcsr_cg/cp_hcsr_access

misa_acc

The misa CSR is a WARL read-write register

Sm_mcsr_cg/cp_mcsr_access/misa

misa_always_rd

This register must be readable in any implementation

Sm_mcsr_cg/cp_mcsr_access/misa

misa_csr_implemented

Sm_mcsr_cg/cp_mcsr_access/misa

misa_enc

Sm_mcsr_cg/cp_mcsr_access/misa

misa_mxl_op

The MXL (Machine XLEN) field encodes the native base integer ISA width as shown in [norm:misa_mxl_enc]. If misa is nonzero, the MXL field indicates the effective XLEN in M-mode, a constant termed MXLEN.

Sm_mcsr_cg/cp_mcsr_access/misa

mxlen

Sm_mcsr_cg/cp_mcsr_access/misa

misa_mxl_acc

The MXL field is read-only.

Sm_mcsr_cg/cp_mcsr_access/misa

misa_mxl_enc

MXL|XLEN === 1 2 3|32 64 Reserved ===

Sm_mcsr_cg/cp_mcsr_access/misa

misa_sz

The misa CSR is MXLEN bits wide.

Sm_mcsr_cg/cp_mcsr_access/misa

misa_extensions_enc

The Extensions field encodes the presence of the standard extensions, with a single bit per letter of the alphabet (bit 0 encodes presence of extension \"A\" , bit 1 encodes presence of extension \"B\", through to bit 25 which encodes \"Z\"). Bit|Character|Description === 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25|A B C D E F G H I J K L M N O P Q R S T U V W X Y Z|Atomic extension B extension Compressed extension Double-precision floating-point extension RV32E/64E base ISA Single-precision floating-point extension Reserved Hypervisor extension RV32I/64I base ISA Reserved Reserved Reserved Integer Multiply/Divide extension Tentatively reserved for User-Level Interrupts extension Reserved Tentatively reserved for Packed-SIMD extension Quad-precision floating-point extension Reserved Supervisor mode implemented Reserved User mode implemented Vector extension Reserved Non-standard extensions implemented Reserved Reserved ===

Sm_mcsr_cg/cp_mcsr_access/misa

misa_extensions_warl, misa_extensions_op

The Extensions field is a WARL field that can contain writable bits where the implementation allows the supported ISA to be modified.

Sm_mcsr_cg/cp_mcsr_access/misa

misa_extensions_writable_bits

Sm_mcsr_cg/cp_mcsr_access/misa

misa_extensions_rst

At reset, the Extensions field shall contain the maximal set of supported extensions, and \"I\" shall be selected over \"E\" if both are available. The misa register is reset to enable the maximal set of supported extensions, as described in [misa].

Sm_mcsr_cg/cp_mcsr_access/misa

misa_extensions_disabling

When a standard extension is disabled by clearing its bit in misa, the instructions and CSRs defined or modified by the extension revert to their defined or reserved behaviors as if the extension is not implemented.

Out of scope; also untestable without Ssstrict because reserved instructions behavior is UNSPECIFIED

misa_extensions_impl_def

For a given RISC-V execution environment, an instruction, extension, or other feature of the RISC-V ISA is ordinarily judged to be implemented or not by the observable execution behavior in that environment. For example, the F extension is said to be implemented for an execution environment if and only if the instructions that the RISC-V Unprivileged ISA defines for F execute as specified.

Tested by executing all of the extensions being certified

misa_extensions_disabling_def

With this definition of implemented, disabling an extension by clearing its bit in misa results in the extension being considered not implemented in M-mode. For example, setting misa.F=0 results in the F extension being not implemented for M-mode, because the F extension’s instructions will not act as the Unprivileged ISA requires but may instead raise an illegal-instruction exception.

Out of scope; also untestable without Ssstrict because reserved instructions behavior is UNSPECIFIED

misa_extensions_rsv_ret_0

All bits that are reserved for future use must return zero when read.

Sm_mcsr_cg/cp_mcsr_access/misa

misa_i_op

The \"I\" bit will be set for the RV32I and RV64I base ISAs

Sm_mcsr_cg/cp_mcsr_access/misa

misa_e_op

the \"E\" bit will be set for RV32E and RV64E.

Sm_mcsr_cg/cp_mcsr_access/misa

misa_x_op

The \"X\" bit will be set if there are any non-standard extensions.

Non-standard extensions are not certified

misa_b_op

When the \"B\" bit is 1, the implementation supports the instructions provided by the Zba, Zbb, and Zbs extensions.

Sm_mcsr_cg/cp_mcsr_access/misa and tests for Zba, Zbb, Zbs

misa_m_op

When the \"M\" bit is 1, the implementation supports all multiply and division instructions defined by the M extension.

Sm_mcsr_cg/cp_mcsr_access/misa and tests for M

misa_s_op

When the \"S\" bit is 1, the implementation supports supervisor mode.

Sm_mcsr_cg/cp_mcsr_access/misa and tests for S

misa_u_op

When the \"U\" bit is 1, the implementation supports user mode.

Sm_mcsr_cg/cp_mcsr_access/misa and tests for U

misa-c_set

MISA.C is set if the following extensions are selected: Zca and not F Zca, Zcf and F (but not D) is specified (RV32 only) Zca, Zcf and Zcd if D is specified (RV32 only) this configuration excludes Zcmp, Zcmt Zca, Zcd if D is specified (RV64 only) this configuration excludes Zcmp, Zcmt

Sm_mcsr_cg/cp_mcsr_access/misa

misa_e_not_i

Unless misa is all read-only zero, the \"E\" bit always reads as the complement of the \"I\" bit.

Sm_mcsr_cg/cp_mcsr_access/misa

Zmmul_misa_m

if the Zmmul extension is supported then the multiply instructions it specifies are supported irrespective of the value of the \"M\" bit.

Sm_mcsr_cg/cp_mcsr_access/misa and tests for Zmmul

misa_e_acc

The \"E\" bit is read-only.

Sm_mcsr_cg/cp_mcsr_access/misa

misa_extensions_dependencies

If an ISA feature x depends on an ISA feature y, then attempting to enable feature x but disable feature y results in both features being disabled.

cp_mcsr_cg/cp_mcsrwalk/misa (clearing F, D, U bits)

misa_inc_ialign

Writing misa may increase IALIGN, e.g., by disabling the \"C\" extension. If an instruction that would write misa increases IALIGN, and the subsequent instruction’s address is not IALIGN-bit aligned, the write to misa is suppressed, leaving misa unchanged.

Out of scope

mvendorid_sz, mvendorid_acc, mvendorid_op

The mvendorid CSR is a 32-bit read-only register providing the JEDEC manufacturer ID of the provider of the core.

Sm_mcsr_cg/cp_mcsr_access/mvendorid

vendor_id_bank

Sm_mcsr_cg/cp_mcsr_access/mvendorid

vendor_id_offset

Sm_mcsr_cg/cp_mcsr_access/mvendorid

mvendorid_always_rd

This register must be readable in any implementation, but a value of 0 can be returned to indicate the field is not implemented or that this is a non-commercial implementation.

Sm_mcsr_cg/cp_mcsr_access/mvendorid

mvendorid_enc

JEDEC manufacturer IDs are ordinarily encoded as a sequence of one-byte continuation codes 0x7f, terminated by a one-byte ID not equal to 0x7f, with an odd parity bit in the most-significant bit of each byte. mvendorid encodes the number of one-byte continuation codes in the Bank field, and encodes the final byte in the Offset field, discarding the parity bit.

Sm_mcsr_cg/cp_mcsr_access/mvendorid

marchid_sz, marchid_acc, marchid_op

The marchid CSR is an MXLEN-bit read-only register encoding the base microarchitecture of the hart.

Sm_mcsr_cg/cp_mcsr_access/marchid

arch_id

Sm_mcsr_cg/cp_mcsr_access/marchid

marchid_always_rd

This register must be readable in any implementation, but a value of 0 can be returned to indicate the field is not implemented.

Sm_mcsr_cg/cp_mcsr_access/marchid

mimpid_op

The mimpid CSR provides a unique encoding of the version of the processor implementation.

Sm_mcsr_cg/cp_mcsr_access/mimpid

imp_id

Sm_mcsr_cg/cp_mcsr_access/mimpid

mimpid_always_rd

This register must be readable in any implementation, but a value of 0 can be returned to indicate that the field is not implemented.

Sm_mcsr_cg/cp_mcsr_access/mimpid

mhartid_sz, mhartid_acc, mhartid_op

The mhartid CSR is an MXLEN-bit read-only register containing the integer ID of the hardware thread running the code.

Sm_mcsr_cg/cp_mcsr_access/mhartid

hart_id

Sm_mcsr_cg/cp_mcsr_access/mhartid

mhartid_always_rd

This register must be readable in any implementation.

Sm_mcsr_cg/cp_mcsr_access/mhartid

mhartid_one_is_zero

one hart must have a hart ID of zero.

Sm_mcsr_cg/cp_mcsr_access/mhartid but only one hart is tested

mhartid_unique

Hart IDs must be unique within the execution environment.

Sm_mcsr_cg/cp_mcsr_access/mhartid but only one hart is tested

mstatus_sz, mstatus_acc

The mstatus register is an MXLEN-bit read/write register formatted as shown in [mstatusreg-rv32] for RV32 and [mstatusreg] for RV64.

Sm_mcsr_cg/cp_mcsr_access/mstatus

mstatush_sz, mstatush_acc

For RV32 only, mstatush is a 32-bit read/write register formatted as shown in [mstatushreg].

Sm_mcsr_cg/cp_mcsr_access/mstatush

mstatus_xie_xret_op, mstatus_xpie_xret_op, mstatus_xpp_xret_op, mstatus_mprv_xret_op

When executing an xRET instruction, supposing xPP holds the value y, xIE is set to xPIE; the privilege mode is changed to y; xPIE is set to 1; and xPP is set to the least-privileged supported mode (U if U-mode is implemented, else M). If y≠M, xRET also sets MPRV=0.

Sm_mprivinst_cg/{cp_mret, cp_sret}

mstatush_enc

Bits 30:4 of mstatush generally contain the same fields found in bits 62:36 of mstatus for RV64. Fields SD, SXL, and UXL do not exist in mstatush.

Sm_mcsr_cg/cp_mcsr_access/mstatush

mstatus_sie_rdonly0, mstatus_spie_rdonly0

If supervisor mode is not implemented, then SIE and SPIE are read-only 0.

Sm_mcsr_cg/cp_mcsr_access/mstatush

mstatus_xpp_enc

The xPP fields can only hold privilege modes up to x

Sm_mcsr_cg/cp_mcsr_access/mstatus

mstatus_mpp_sz

MPP is two bits wide

Sm_mcsr_cg/cp_mcsr_access/mstatus

mstatus_xpp_warl

Sm_mcsr_cg/{cp_mcsr_access,cp_mcsrwalk}/mstatus

mstatus_xpp_rdonly0

If privilege mode x is not implemented, then xPP must be read-only 0.

Sm_mcsr_cg/cp_mcsr_access/mstatus

mstatus_spp_sz

SPP is one bit wide.

Sm_mcsr_cg/cp_mcsr_access/mstatus

mstatus_mdt_sz, mstatus_mdt_warl

The M-mode-disable-trap (MDT) bit is a WARL field introduced by the Smdbltrp extension.

Sm_mcsr_cg/cp_mcsr_access/mstatus

mstatus_sxl_warl, mstatus_uxl_warl, mstatus_sxl_op, mstatus_uxl_op

For RV64 harts, the SXL and UXL fields are WARL fields that control the value of XLEN for S-mode and U-mode, respectively.

Sm_mcsr_cg/cp_mcsr_access/mstatus

mstatus_sxl_enc, mstatus_uxl_enc

For RV64 harts, the SXL and UXL fields are WARL fields that control the value of XLEN for S-mode and U-mode, respectively. The encoding of these fields is the same as the MXL field of misa, shown in [norm:misa_mxl_enc].

Out of scope

mstatus_sxl_exist_mxlen32, mstatus_uxl_exist_mxlen32

When MXLEN=32, the SXL and UXL fields do not exist, and SXLEN=32 and UXLEN=32.

Sm_mcsr_cg/cp_mcsr_access/mstatus

mstatus_sxl_acc_mxlen64

When MXLEN=64, if S-mode is not supported, then SXL is read-only zero. Otherwise, it is a WARL field that encodes the current value of SXLEN.

Sm_mcsr_cg/cp_mcsr_access/mstatus

mstatus_sxl_rdonly_mxlen64

Sm_mcsr_cg/cp_mcsr_access/mstatus

mstatus_uxl_acc_mxlen64

When MXLEN=64, if U-mode is not supported, then UXL is read-only zero. Otherwise, it is a WARL field that encodes the current value of UXLEN.

Sm_mcsr_cg/cp_mcsr_access/mstatus

mstatus_uxl_rdonly_mxlen64

an implementation may make UXL be a read-only field whose value always ensures that UXLEN=MXLEN or UXLEN=SXLEN.

Sm_mcsr_cg/cp_mcsr_access/mstatus

mstatus_uxl_legal_vals_smode

Sm_mcsr_cg/cp_mcsr_access/mstatus

mstatus_mprv_ldst_op

When MPRV=0, explicit memory accesses behave as normal, using the translation and protection mechanisms of the current privilege mode. When MPRV=1, load and store memory addresses are translated and protected, and endianness is applied, as though the current privilege mode were set to MPP.

Sv_cg/{ms.2, ms.3, ms.4}, PMPS_cg/cp_mprv, PMPU_cg/cp_mprv

mstatus_mprv_inst_xlat_op

Instruction address-translation and protection are unaffected by the setting of MPRV.

Sv_cg/{ms.2, ms.3, ms.4}, PMPS_cg/cp_mprv, PMPU_cg/cp_mprv

mstatus_mprv_rdonly0_no_umode

MPRV is read-only 0 if U-mode is not supported.

Sm_mcsr_cg/cp_mcsr_access/mstatus

mstatus_mprv_clr_mret_sret_less_priv

An MRET or SRET instruction that changes the privilege mode to a mode less privileged than M also sets MPRV=0.

{Sm_mprivinst_cg/S_sprivinst_cg}/{cp_mret, cp_sret}

mstatus_mxr_op

When MXR=0, only loads from pages marked readable (R=1 in [sv32pte]) will succeed. When MXR=1, loads from pages marked either readable or executable (R=1 or X=1) will succeed. MXR has no effect when page-based virtual memory is not in effect.

Sv_cg/{pte.11,pte.12}

mstatus_mxr_rdonly0_no_smode

MXR is read-only 0 if S-mode is not supported.

Sm_mcsr_cg/cp_mcsr_access/mstatus

mstatus_sum_op

When SUM=0, S-mode memory accesses to pages that are accessible by U-mode (U=1 in [sv32pte]) will fault. When SUM=1, these accesses are permitted.

Sv_cg/{ms.3, ms.4, pte.5, pte.6, pte.8, pte.9

mstatus_sum_op_no-vm

SUM has no effect when page-based virtual memory is not in effect.

TODO

mstatus_sum_op_mprv_mpp

while SUM is ordinarily ignored when not executing in S-mode, it is in effect when MPRV=1 and MPP=S.

Sv_cg/{ms.3, ms.4}

mstatus_sum_rdonly0

SUM is read-only 0 if S-mode is not supported or if satp.MODE is read-only 0.

Sm_mcsr_cg/cp_mcsr_access/mstatus

mstatus_mxr_sum_op_acc_fault

TODO by UET: add to {PMPSm/PMPS/PMPU}_cg/cp_cfg_RW tests

mstatus_mbe_warl, mstatus_sbe_warl, mstatus_ube_warl, mstatush_mbe_warl, mstatush_sbe_warl, mstatush_ube_warl

Sm_mcsr_cg/cp_mcsr_access/mstatus, Sm_mcsr_cg/cp_mcsr_access/mstatush

mstatus_tvm_warl

Sm_mcsr_cg/cp_mcsr_access/mstatus

mstatus_tvm_op

The TVM (Trap Virtual Memory) bit is a WARL field that supports intercepting supervisor virtual-memory management operations. When TVM=1, attempts to read or write the satp CSR or execute an SFENCE.VMA or SINVAL.VMA instruction while executing in S-mode will raise an illegal-instruction exception. When TVM=0, these operations are permitted in S-mode. TVM is read-only 0 when S-mode is not supported.

Sv_cg/ms.1, Svinval_cg/cp_svinval

mstatus_tw_acc

TW is read-only 0 when there are no modes less privileged than M.

Sm_mcsr_cg/cp_mcsr_access/mstatus

mstatus_tsr_warl

Sm_mcsr_cg/cp_mcsr_access/mstatus

mstatus_tsr_op

When TSR=1, attempts to execute SRET while executing in S-mode will raise an illegal-instruction exception. When TSR=0, this operation is permitted in S-mode.

Sm_mprivinst/cp_sret

mstatus_tsr_acc

Sm_mcsr_cg/cp_mcsr_access/mstatus

mstatus_fs_warl, mstatus_vs_warl

Sm_mcsr_cg/cp_mcsr_access/mstatus, Sm_mcsr_cg/cp_mcsrwalk/mstatus

mstatus_fs_op

The FS field encodes the status of the floating-point unit state, including the floating-point registers f0–f31 and the CSRs fcsr, frm, and fflags.

SmF_cg/cp_mstatus_FS_transition

mstatus_vs_op

The VS field encodes the status of the vector extension state, including the vector registers v0–v31 and the CSRs vcsr, vxrm, vxsat, vstart, vl, vtype, and vlenb.

TODO: test with vector

mstatus_xs_op

The XS field encodes the status of additional user-mode extensions and associated state. The XS field represents a summary of all extensions' status as shown in [norm:mstatus_fs_vs_xs_enc].

Untested

mstatus_fs_enc, mstatus_vs_enc, mstatus_xs_enc

Status|FS and VS Meaning|XS Meaning === 0 1 2 3|Off Initial Clean Dirty|All off None dirty or clean, some on None dirty, some clean Some dirty ===

Sm_mcsr_cg/cp_mcsr_access/mstatus, SmF_cg/cp_mstatus_FS_transition

mstatus_fs_acc

If the F extension is implemented, the FS field shall not be read-only zero. If neither the F extension nor S-mode is implemented, then FS is read-only zero.

Sm_mcsr_cg/cp_mcsr_access/mstatus

mstatus_fs_rdonly0_s-no-f

Sm_mcsr_cg/cp_mcsr_access/mstatus

mstatus_vs_acc

If the v registers are implemented, the VS field shall not be read-only zero. If neither the v registers nor S-mode is implemented, then VS is read-only zero.

Sm_mcsr_cg/cp_mcsr_access/mstatus

mstatus_vs_rdonly0_s-no-v

TODO

mstatus_xs_acc

In harts without additional user extensions requiring new state, the XS field is read-only zero.

Sm_mcsr_cg/cp_mcsr_access/mstatus

mstatus_xs_equiv

Every additional extension with state provides a CSR field that encodes the equivalent of the XS states.

Out of scope

mstatus_sd_acc

The SD bit is a read-only bit

Sm_mstatus_cg/cp_mstatus_sd_write

mstatus_sd_op

summarizes whether either the FS, VS, or XS fields signal the presence of some dirty state that will require saving extended user context to memory.

Sm_mstatus_cg/cp_mstatus_sd_write

mstatus_sd_rdonly0

If FS, XS, and VS are all read-only zero, then SD is also always zero.

Sm_mstatus_cg/cp_mstatus_sd_write

mstatus_fs_vs_xs_off_op

When an extension’s status is set to Off, any instruction that attempts to read or write the corresponding state will cause an illegal-instruction exception.

SmF_cg/{cp_fcsrwalk, cp_frm_walk, cp_fflags_walk, cp_mstatus_FS_transition}, TODO for Vector

mstatus_fs_vs_xs_initial_op

When the status is Initial, the corresponding state should have an initial constant value.

TODO: test with float, vector

mstatus_fs_vs_xs_clean_op

When the status is Clean, the corresponding state is potentially different from the initial value, but matches the last value stored on a context swap.

Untestable

mstatus_fs_vs_xs_dirty_op

When the status is Dirty, the corresponding state has potentially been modified since the last context save.

cp_mstatus_FS_transition

mstatus_fs_vs_xs_update_indep_priv

The status fields will also be updated during execution of instructions, regardless of privilege mode.

TODO: test with float, vector

mstatus_fs_wr

Changing the setting of FS has no effect on the contents of the floating-point register state. In particular, setting FS=Off does not destroy the state, nor does setting FS=Initial clear the contents.

TODO: test with float

mstatus_vs_wr

the setting of VS has no effect on the contents of the vector register state.

TODO: test with vector

mstatus_fs_imprecise

Untestable. TODO: imprecise dirty tracking could be a problem to match the reference model in cp_mstatus_FS_transition

mstatus_fs_no_dirty_track

SmF_cg/{cp_fcsr_frm_write, cp_mstatus_FS_transition}

mstatus_fs_no_change_dirty

Untestable without UDB parameters to control this behavior in the ref model

mstatus_vs_imprecise

Untestable

mstatus_vs_no_change_dirty

Untestable

mtvec_enc

Sm_mcsr_cg/cp_mcsr_access/mtvec

mtvec_sz, mtvec_warl, mtvec_acc

The mtvec register is an MXLEN-bit WARL read/write register that holds trap vector configuration, consisting of a vector base address (BASE) and a vector mode (MODE).

Sm_mcsr_cg/cp_mcsr_access/mtvec

mtvec_mandatory

The mtvec register must always be implemented

Sm_mcsr_cg/cp_mcsr_access/mtvec

mtvec_rdonly

Sm_mcsr_cg/cp_mcsr_access/mtvec

mtvec_base_align_4B

The value in the BASE field must always be aligned on a 4-byte boundary

Sm_mcsr_cg/cp_mcsr_access/mtvec

mtvec_base_align_func_mode

Sm_mcsr_cg/cp_mcsr_access/mtvec

medelegh_sz_xlen32, medelegh_acc_xlen32, medelegh_enc_xlen32

When XLEN=32, medelegh is a 32-bit read/write register that aliases bits 63:32 of medeleg.

Sm_mcsr_cg/cp_mcsr_access/medelegh

medelegh_enc_xlen32

When XLEN=32, medelegh is a 32-bit read/write register that aliases bits 63:32 of medeleg.

Sm_mcsr_cg/cp_mcsr_access/medelegh

medelegh_omit_xlen64

Untested except in Sstrict* because nonexistent register behavior is UNSPECIFIED

'medeleg_sz', 'medeleg_acc'

Sm_mcsr_cg/cp_mcsr_access/medeleg

'mideleg_sz', 'mideleg_acc'

Sm_mcsr_cg/cp_mcsr_access/mideleg

'medeleg_mandatory_S-mode', 'mideleg_mandatory_S-mode'

Sm_mcsr_cg/cp_mcsr_access/{medeleg/mideleg

'medeleg_omit_wo_S-mode', 'mideleg_omit_wo_S-mode'

Sm_mcsr_cg/cp_mcsr_access/{medeleg/mideleg

'medeleg_warl', 'mideleg_warl'

Sm_mcsr_cg/cp_mcsr_access/mideleg

medeleg_no_rd1

An implementation shall not have any bits of medeleg be read-only one

Sm_mcsr_cg/cp_mcsr_access/medeleg

mideleg_no_rd1

an implementation shall not fix as read-only one any bits of mideleg corresponding to machine-level interrupts

Sm_mcsr_cg/cp_mcsr_access/mideleg

mideleg_rd1_lower_level

Sm_mcsr_cg/cp_mcsr_access/mideleg

medeleg_when_rd0

For exceptions that cannot occur in less privileged modes, the corresponding medeleg bits should be read-only zero. In particular, medeleg[11] is read-only zero.

Sm_mcsr_cg/cp_mcsr_access/medeleg

medeleg_16_no_rd0

The medeleg[16] is read-only zero as double trap is not delegatable.

Sm_mcsr_cg/cp_mcsr_access/medeleg

mip_sz, mip_acc

The mip register is an MXLEN-bit read/write register containing information on pending interrupts

Sm_mcsr_cg/cp_mcsr_access/mip

mie_sz, mie_acc

mie is the corresponding MXLEN-bit read/write register containing interrupt enable bits.

Sm_mcsr_cg/cp_mcsr_access/mie

mip_bits_wr_or_rdonly

Sm_mcsr_cg/cp_mcsrwalk/mip

mie_bits_wr

A bit in mie must be writable if the corresponding interrupt can ever become pending.

Sm_mcsr_cg/cp_mcsrwalk/mie

mie_bits_rdonly0

Bits of mie that are not writable must be read-only zero.

Sm_mcsr_cg/cp_mcsrwalk/mie

mip_msip_maybe_rdonly0, mie_msie_maybe_rdonly0

Sm_mcsr_cg/cp_mcsrwalk/{mip,mie}

mip_seip_rdonly0, mip_stip_rdonly0, mip_ssip_rdonly0, mie_seie_rdonly0, mie_stie_rdonly0, mie_ssie_rdonly0

If supervisor mode is not implemented, bits SEIP, STIP, and SSIP of mip and SEIE, STIE, and SSIE of mie are read-only zeros.

Sm_mcsr_cg/cp_mcsrwalk/{mip,mie}

mip_lcofip_acc

LCOFIP is read-write in mip

Sm_mcsr_cg/cp_mcsrwalk/{mip,mie}

mip_lcofip_rdonly0, mie_lcofie_rdonly0

If the Sscofpmf extension is not implemented, mip.LCOFIP and mie.LCOFIE are read-only zeros.

Sm_mcsr_cg/cp_mcsrwalk/{mip,mie}

menvcfg-stce

Sm_mcsr_cg/cp_mcsrwalk/menvcfg

menvcfg-cbze

Sm_mcsr_cg/cp_mcsrwalk/menvcfg, Zicboz_cg/{zero.1, zero.2, zero.4, zero.5}

menvcfg-cbcfe

Sm_mcsr_cg/cp_mcsrwalk/menvcfg, Zicbom_cg/{cl.1, cl.4, fl.1, fl.4}

menvcfg-cbie

Sm_mcsr_cg/cp_mcsrwalk/menvcfg, Zicbom_cg/{inv.1, inv.4, inv.6}

cbo-inval_m-mode_op

Zicbom_cg/{inv.1, inv.4, inv.6}

mcycle_op

The mcycle CSR counts the number of clock cycles executed by the processor core on which the hart is running.

Sm_mcsr_cg/cp_cntr_access/mcycle

mcycle_sz

The mcycle and minstret registers have 64-bit precision on all RV32 and RV64 harts.

Sm_mcsr_cg/cp_cntr_access/mcycle

mcycle_rst

The counter registers have an arbitrary value after the hart is reset, and can be written with a given value.

Sm_mcsr_cg/cp_cntr_access/mcycle

mcycle_wr

Any CSR write takes effect after the writing instruction has otherwise completed.

Sm_mcsr_cg/cp_cntr_access

mcycle_shared

Not tested; requires multi-hart core

mcycleh_op, minstreth_op, mhpmcounterh_op, mhpmeventh_op

reads of the mcycleh, minstreth, mhpmcounternh, and mhpmeventnh CSRs return bits 63-32 of the corresponding register, and writes change only bits 63-32.

Sm_mcsr_cg/cp_cntr_access/{mcycleh,minstreth,mhpmcounterh,mhpmeventh}

minstret_op

The minstret CSR counts the number of instructions the hart has retired.

Sm_mcsr_cg/cp_cntr_access/minstret

minstret_sz

The mcycle and minstret registers have 64-bit precision on all RV32 and RV64 harts.

Sm_mcsr_cg/cp_cntr_access

minstret_rst

The counter registers have an arbitrary value after the hart is reset, and can be written with a given value.

Sm_mcsr_cg/cp_cntr_access/minstret

minstret_wr

Any CSR write takes effect after the writing instruction has otherwise completed.

Sm_mcsr_cg/cp_cntr_access

mhpmcounter_num

The hardware performance monitor includes 29 additional 64-bit event counters, mhpmcounter3-mhpmcounter31.

Sm_mcsr_cg/cp_cntr_access

mhpmcounter_warl

Sm_mcsr_cg/cp_cntr_access

mhpmcounter_mandatory

All counters should be implemented

Sm_mcsr_cg/cp_cntr_access

mhpmcounter3_rdonly0, mhpmcounter4_rdonly0, mhpmcounter5_rdonly0, mhpmcounter6_rdonly0, mhpmcounter7_rdonly0, mhpmcounter8_rdonly0, mhpmcounter9_rdonly0, mhpmcounter10_rdonly0, mhpmcounter11_rdonly0, mhpmcounter12_rdonly0, mhpmcounter13_rdonly0, mhpmcounter14_rdonly0, mhpmcounter15_rdonly0

Sm_mcsr_cg/cp_cntr_access

mhpmcounter16_rdonly0, mhpmcounter17_rdonly0, mhpmcounter18_rdonly0, mhpmcounter19_rdonly0, mhpmcounter20_rdonly0, mhpmcounter21_rdonly0, mhpmcounter22_rdonly0, mhpmcounter23_rdonly0, mhpmcounter24_rdonly0, mhpmcounter25_rdonly0, mhpmcounter26_rdonly0, mhpmcounter27_rdonly0, mhpmcounter28_rdonly0, mhpmcounter29_rdonly0, mhpmcounter30_rdonly0, mhpmcounter31_rdonly0

Sm_mcsr_cg/cp_cntr_access

mhpmcounter3_sz, mhpmcounter4_sz, mhpmcounter5_sz, mhpmcounter6_sz, mhpmcounter7_sz, mhpmcounter8_sz, mhpmcounter9_sz, mhpmcounter10_sz, mhpmcounter11_sz, mhpmcounter12_sz, mhpmcounter13_sz, mhpmcounter14_sz, mhpmcounter15_sz

Sm_mcsr_cg/cp_cntr_access

mhpmcounter16_sz, mhpmcounter17_sz, mhpmcounter18_sz, mhpmcounter19_sz, mhpmcounter20_sz, mhpmcounter21_sz, mhpmcounter22_sz, mhpmcounter23_sz, mhpmcounter24_sz, mhpmcounter25_sz, mhpmcounter26_sz, mhpmcounter27_sz, mhpmcounter28_sz, mhpmcounter29_sz, mhpmcounter30_sz, mhpmcounter31_sz

Sm_mcsr_cg/cp_cntr_access

mhpmevent_sz, mhpmevent_warl, mhpmevent_op

The event selector CSRs, mhpmevent3-mhpmevent31, are 64-bit WARL registers that control which event causes the corresponding counter to increment.

Sm_mcsr_cg/cp_mcsr_access

mhpmevent_enc

The meaning of these events is defined by the platform, but event 0 is defined to mean \"no event.\"

TODO: check no counting on event 0

mhpmevent3_rdonly0, mhpmevent4_rdonly0, mhpmevent5_rdonly0, mhpmevent6_rdonly0, mhpmevent7_rdonly0, mhpmevent8_rdonly0, mhpmevent9_rdonly0, mhpmevent10_rdonly0, mhpmevent11_rdonly0, mhpmevent12_rdonly0, mhpmevent13_rdonly0, mhpmevent14_rdonly0, mhpmevent15_rdonly0

Sm_mcsr_cg/cp_mcsr_access

mhpmevent16_rdonly0, mhpmevent17_rdonly0, mhpmevent18_rdonly0, mhpmevent19_rdonly0, mhpmevent20_rdonly0, mhpmevent21_rdonly0, mhpmevent22_rdonly0, mhpmevent23_rdonly0, mhpmevent24_rdonly0, mhpmevent25_rdonly0, mhpmevent26_rdonly0, mhpmevent27_rdonly0, mhpmevent28_rdonly0, mhpmevent29_rdonly0, mhpmevent30_rdonly0, mhpmevent31_rdonly0

Sm_mcsr_cg/cp_mcsr_access

mcounteren_cy_rdonly0, mcounteren_tm_rdonly0, mcounteren_ir_rdonly0, mcounteren_hpm3_rdonly0, mcounteren_hpm4_rdonly0, mcounteren_hpm5_rdonly0, mcounteren_hpm6_rdonly0, mcounteren_hpm7_rdonly0, mcounteren_hpm8_rdonly0, mcounteren_hpm9_rdonly0, mcounteren_hpm10_rdonly0, mcounteren_hpm11_rdonly0, mcounteren_hpm12_rdonly0, mcounteren_hpm13_rdonly0, mcounteren_hpm14_rdonly0, mcounteren_hpm15_rdonly0

Sm_mcsr_cg/cp_mcsr_access/mcounteren

mcounteren_hpm16_rdonly0, mcounteren_hpm17_rdonly0, mcounteren_hpm18_rdonly0, mcounteren_hpm19_rdonly0, mcounteren_hpm20_rdonly0, mcounteren_hpm21_rdonly0, mcounteren_hpm22_rdonly0, mcounteren_hpm23_rdonly0, mcounteren_hpm24_rdonly0, mcounteren_hpm25_rdonly0, mcounteren_hpm26_rdonly0, mcounteren_hpm27_rdonly0, mcounteren_hpm28_rdonly0, mcounteren_hpm29_rdonly0, mcounteren_hpm30_rdonly0, mcounteren_hpm31_rdonly0

Sm_mcsr_cg/cp_mcsr_access/mcounteren

mcounteren_presence

In harts without U-mode, the mcounteren register should not exist.

Untestable because nonexistent registers are reserved and unspecified except in SsstrictM

cycle_op, instret_op, hpmcounter_op, cycle_rdonly, instret_rdonly, hpmcounter_rdonly

The cycle, instret, and hpmcountern CSRs are read-only shadows of mcycle, minstret, and mhpmcounter n, respectively.

Zicntr_csrrs_cg/cp_cntr, Zihpm_csrrs_cg/cp_cntr_hpm, Sm_mcsr_cg/cp_csrw_readonly

time_op, time_rdonly

The time CSR is a read-only shadow of the memory-mapped mtime register.

Zicntr_csrrs_cg/cp_cntr/csr_time, Sm_mcsr_cg/cp_mtime_write, Sm_mcsr_cg/cp_csrw_readonly/time

cycleh_op, instreth_op, hpmcounternh_op, cycleh_rdonly, instreth_rdonly, hpmcounternh_rdonly

when XLEN=32, the cycleh, instreth and hpmcounternh CSRs are read-only shadows of mcycleh, minstreth and mhpmcounternh, respectively.

Zicntr_csrrs_cg/cp_cntr, Zihpm_csrrs_cg/cp_cntr_hpm, Sm_mcsr_cg/cp_csrw_readonly

timeh_op, timeh_rdonly

When XLEN=32, the timeh CSR is a read-only shadow of the upper 32 bits of the memory-mapped mtime register

Zicntr_csrrs_cg/cp_cntr/csr_timeh, Sm_mcsr_cg/cp_mtimeh_write, Sm_mcsr_cg/cp_csrw_readonly

mcountinhibit_enc

Sm_mcsr_cg/cp_mcsr_access/mcountinhibit

mcountinhibit_sz, mcountinhibit_warl

The counter-inhibit register mcountinhibit is a 32-bit WARL register that controls which of the hardware performance-monitoring counters increment.

Sm_mcsr_cg/cp_mcsr_access/mcountinhibit

mcountinhibit_only_inc

The settings in this register only control whether the counters increment; their accessibility is not affected by the setting of this register.

TODO

mcountinhibit_op

The counter-inhibit register mcountinhibit is a 32-bit WARL register that controls which of the hardware performance-monitoring counters increment. When the CY, IR, or HPMn bit in the mcountinhibit register is clear, the mcycle, minstret, or mhpmcountern register increments as usual. When the CY, IR, or HPMn bit is set, the corresponding counter does not increment.

Sm_mcsr_cg/cp_inhibit_{mcycle/minstret}. Other registers do not increment predictably and thus are untested.

mcountinhibit_cy_shared

The mcycle CSR may be shared between harts on the same core, in which case the mcountinhibit.CY field is also shared between those harts, and so writes to mcountinhibit.CY will be visible to those harts.

Untested because requires multi-hart core

mcountinhibit_not_impl

If the mcountinhibit register is not implemented, the implementation behaves as though the register were set to zero.

Sm_mcsr_cg/cp_inhibit_{mcycle/minstret}

mscratch_sz, mscratch_acc

The mscratch register is an MXLEN-bit read/write register dedicated for use by machine mode.

Sm_mcsr_cg/cp_mcsr_access/mscratch

mscratch_enc

Sm_mcsr_cg/cp_mcsr_access/mscratch

mepc_sz, mepc_acc

mepc is an MXLEN-bit read/write register

Sm_mcsr_cg/cp_mcsr_access/mepc

mepc_align

The low bit of mepc (mepc[0]) is always zero. On implementations that support only IALIGN=32, the two low bits (mepc[1:0]) are always zero.

Sm_mcsr_cg/cp_mcsr_access/mepc

mepc_bit1_dyn_ialign_op

If an implementation allows IALIGN to be either 16 or 32 (by changing CSR misa, for example), then, whenever IALIGN=32, bit mepc[1] is masked on reads so that it appears to be 0. This masking occurs also for the implicit read by the MRET instruction. Though masked, mepc[1] remains writable when IALIGN=32.

Out of scope.

mepc_warl

Sm_mcsr_cg/cp_mcsr_access/mepc

mepc_inv_addr_conv

Sm_mcsr_cg/cp_mcsr_access/mepc

mepc_enc

Sm_mcsr_cg/cp_mcsr_access/mepc

mcause_sz, mcause_acc

The mcause register is an MXLEN-bit read-write register

Sm_mcsr_cg/cp_mcsr_access/mcause

mcause_enc

Sm_mcsr_cg/cp_mcsr_access/mcause

mcause_exccode_enc

Interrupt|Exception Code|Description === 1 1 1 1|0 1 2 3|Reserved Supervisor software interrupt Reserved Machine software interrupt¶1 1 1 1|4 5 6 7|Reserved Supervisor timer interrupt Reserved Machine timer interrupt¶1 1 1 1|8 9 10 11|Reserved Supervisor external interrupt Reserved Machine external interrupt¶1 1 1 1|12 13 14-15 ≥16|Reserved Counter-overflow interrupt Reserved Designated for platform use¶0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0|0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20-23 24-31 32-47 48-63 ≥64|Instruction address misaligned Instruction access fault Illegal instruction Breakpoint Load address misaligned Load access fault Store/AMO address misaligned Store/AMO access fault Environment call from U-mode Environment call from S-mode Reserved Environment call from M-mode Instruction page fault Load page fault Reserved Store/AMO page fault Double trap Reserved Software check Hardware error Reserved Designated for custom use Reserved Designated for custom use Reserved ===

See mcause_op

mcause_exccode_wlrl

Sm_mcause_cg/{cp_mcause_write_exception, cp_mcause_write_interrupt}

SXLEN, UXLEN

The effective XLEN in S-mode and U-mode are termed SXLEN and UXLEN, respectively. When MXLEN=32, the SXL and UXL fields do not exist, and SXLEN=32 and UXLEN=32.

Sm_mcsr_cg/cp_mcsr_access/mstatus

xlen_reduction_op

Whenever XLEN in any mode is set to a value less than the widest supported XLEN, all operations must ignore source operand register bits above the configured XLEN, and must sign-extend results to fill the entire widest supported XLEN in the destination register. Similarly, pc bits above XLEN are ignored, and when the pc is written, it is sign-extended to fill the widest supported XLEN.

NOT TESTED

xlen_reduction_hint_op

Out of scope

endianness_inst_fetch_little

Instruction fetches are always little-endian.

Tested by executing instructions

reset_addr

Tested with linker script

nmi_addr

Out of scope

trap_del_S-mode_no_M-mode

When a trap is delegated to S-mode The mcause, mepc, and mtval registers and the MPP and MPIE fields of mstatus are not written.

Untested; S-mode handler does not have access to M-mode CSRs and changing to M-mode disturbs CSRs
Table 130. Sm UDB Parameters
Parameter Description Coverpoint Effect

MXLEN

XLEN in machine mode, specified in bits

all tests

Implicitly tested by all the XLEN-dependent tests (e.g. add would fail if XLEN is wrong)

MISA_CSR_IMPLEMENTED

Options:

true:: The misa CSR returns a non-zero value.

false:: The misa CSR is read-only-0.

cp_mcsr_access

misa bin results depend on parameter

TIME_CSR_IMPLEMENTED

Whether or not a real hardware time CSR exists. Implementations can either provide a real CSR or emulate access at M-mode.

Possible values:

true:: time/timeh exists, and accessing it will not cause an IllegalInstruction trap

false:: time/timeh does not exist. Accessing the CSR will cause an IllegalInstruction trap or enter an unpredictable state, depending on TRAP_ON_UNIMPLEMENTED_CSR. Privileged software may emulate the time CSR, or may pass the exception to a lower level.

cp_mtime_write

coverpoint only applies if parameter is True

COUNTINHIBIT_EN

Indicates which hardware performance monitor counters can be disabled from mcountinhibit.

An unimplemented counter cannot be specified, i.e., if HPM_COUNTER_EN[3] is false, it would be illegal to set COUNTINHIBIT_EN[3] to true.

COUNTINHIBIT_EN[1] can never be true, since it corresponds to mcountinhibit.TM, which is always read-only-0.

cp_inhibit

bins 0 and 2 for mcycle and minstret are affected by this parameter. Other bins are OUT-OF-SCOPE and not tested because HPM behavior is UNSPECIFIED

MARCHID_IMPLEMENTED

* false: marchid is not implemented, and must be read-only-0 * true: marchid is implemented, and the value is determined by ARCH_ID_VALUE

cp_mcsr_access

if false, marchid bin is read-only zero

ARCH_ID_VALUE

The value of marchid The combination of mvendorid and marchid should uniquely identify the type of hart microarchitecture that is implemented.

cp_mcsr_access

marchid value

MIMPID_IMPLEMENTED

* false: mimpid is not implemented, and must be read-only-0 * true: mimpid is implemented, and the value is determined by IMP_ID_VALUE

cp_mcsr_access

if false, mimpid is read-only zero.

IMP_ID_VALUE

A unique encoding of the version of the processor implementation.

cp_mcsr_access

mimpid value

VENDOR_ID_BANK

Encodes the number of one-byte continuation codes in the Bank field of mvendorid.

iN JEDEC’s parlance, the bank number is one greater than the number of continuation codes; hence, the mvendorid Bank field encodes a value that is one less than the JEDEC bank number.

cp_mcsr_access

mvendorid value

VENDOR_ID_OFFSET

Encodes the final byte of a JEDEC manufactor ID, discarding the parity bit.

cp_mcsr_access

mvendorid value

TODO: Many new normative rules have been added since this was written. Update Sm.yaml.

B.1.2. S Supervisor-Mode CSRs and Instructions

These test additional CSRs that exist in supervisor mode, and privileged instructions in supervisor mode.

Table 131. S Coverpoints

Google Sheet Testplan
Table 132. S Normative Rules
Normative Rule Rule Text Coverpoints

sstatus_sz, sstatus_mode, sstatus_acc

The sstatus register is an SXLEN-bit read/write register formatted as shown in when SXLEN=32 and when SXLEN=64. The sstatus register keeps track of the processor’s current operating state.

S_scsr_cg/cp_scsr_access/sstatus TODO: should xstatus not exercise all bits because of WPRI?

sstatus-spp_sz, sstatus-spp_acc, sstatus-spp_op

The SPP bit indicates the privilege level at which a hart was executing before entering supervisor mode. When a trap is taken, SPP is set to 0 if the trap originated from user mode, or 1 otherwise. When an SRET instruction (see ) is executed to return from the trap handler, the privilege level is set to user mode if the SPP bit is 0, or supervisor mode if the SPP bit is 1; SPP is then set to 0.

S_sprivist_cg/cp_sret_s

sstatus-sie_sz, sstatus-sie_acc, sstatus-sie_op

The SIE bit enables or disables all interrupts in supervisor mode. When SIE is clear, interrupts are not taken while in supervisor mode. When the hart is running in user-mode, the value in SIE is ignored, and supervisor-level interrupts are enabled. The supervisor can disable individual interrupt sources using the sie CSR.

InterruptsS_cg/{cp_priority_mie_s, cp_user_mti}

sstatus-spie_sz, sstatus-spie_acc, sstatus-spie_op

The SPIE bit indicates whether supervisor interrupts were enabled prior to trapping into supervisor mode. When a trap is taken into supervisor mode, SPIE is set to SIE, and SIE is set to 0. When an SRET instruction is executed, SIE is set to SPIE, then SPIE is set to 1.

InterruptsS_cg/cp_user_mti, ExceptionsS_cg/cp_medeleg_msu_illegalinstruction, S_sprivist_cg/cp_sret_s

sstatus-uxl_acc, sstatus-uxl_op

The UXL field controls the value of XLEN for U-mode, termed UXLEN, which may differ from the value of XLEN for S-mode, termed SXLEN. The encoding of UXL is the same as that of the MXL field of misa, shown in .

OUT-OF-SCOPE

sstatus-uxl_sz

When SXLEN=32, the UXL field does not exist, and UXLEN=32. When SXLEN=64, it is a WARL field that encodes the current value of UXLEN. In particular, an implementation may make UXL be a read-only field whose value always ensures that UXLEN=SXLEN.

OUT-OF-SCOPE

sstatus-uxl_behavior

If UXLEN≠SXLEN, instructions executed in the narrower mode must ignore source register operand bits above the configured XLEN, and must sign-extend results to fill the widest supported XLEN in the destination register.

OUT-OF-SCOPE

hint_sxlen

OUT-OF-SCOPE

sstatus-sum_satp-mode

SUM is read-only 0 if satp.MODE is read-only 0.

S_scsr_cg/cp_scsrwalk

stvec_sz, stvec_acc, stvec_mode

The stvec register is an SXLEN-bit read/write register that holds trap vector configuration, consisting of a vector base address (BASE) and a vector mode (MODE).

S_scsr_cg/cp_scsr_access

stvec_op

The BASE field in stvec is a field that can hold any valid virtual or physical address, subject to the following alignment constraints: the address must be 4-byte aligned, and MODE settings other than Direct might impose additional alignment constraints on the value in the BASE field.

S_scsr_cg/cp_scsrwalk

stvec_sz_base

Note that the CSR contains only bits XLEN-1 through 2 of the address BASE. When used as an address, the lower two bits are filled with zeroes to obtain an XLEN-bit address that is always aligned on a 4-byte boundary.

ExceptionsS_cg/cp_stvec

sip_sz, sie_sz, sip_mode, sie_mode

The sip register is an SXLEN-bit read/write register containing information on pending interrupts, while sie is the corresponding SXLEN-bit read/write register containing interrupt enable bits. Interrupt cause number i (as reported in CSR scause, ) corresponds with bit i in both sip and sie. Bits 15:0 are allocated to standard interrupt causes only, while bits 16 and above are designated for platform use.

S_scsr_cg/cp_scsrwalk, InterruptsS_cg/cp_priority_mip_s

sie_sip_supervisor_strap

An interrupt i will trap to S-mode if both of the following are true: (a) either the current privilege mode is S and the SIE bit in the sstatus register is set, or the current privilege mode has less privilege than S-mode; and (b) bit i is set in both sip and sie.

InterruptsS_cg/{cp_priority_both_s, cp_user_mti}

sie_sip_strap_time_constraint

These conditions for an interrupt trap to occur must be evaluated in a bounded amount of time from when an interrupt becomes, or ceases to be, pending in sip, and must also be evaluated immediately following the execution of an SRET instruction or an explicit write to a CSR on which these interrupt trap conditions expressly depend (including sip, sie and sstatus).

TODO

s_interrupt_priority

Interrupts to S-mode take priority over any interrupts to lower privilege modes.

TODO: move to hypervisor VS interrupts

sip_acc

Each individual bit in register sip may be writable or may be read-only.

S_scsr_cg/cp_scsrwalk/sip

sip_op

When bit i in sip is writable, a pending interrupt i can be cleared by writing 0 to this bit. If interrupt i can become pending but bit i in sip is read-only, the implementation must provide some other mechanism for clearing the pending interrupt (which may involve a call to the execution environment).

InterruptsS_cg/cp_trigger_ssi_sip

sie_acc

A bit in sie must be writable if the corresponding interrupt can ever become pending. Bits of sie that are not writable are read-only zero.

S_scsr_cg/cp_scsrwalk/sie, InterruptsS_cg/cp_priority_both_s

sip_sie_bits_sz

The standard portions (bits 15:0) of registers sip and sie are formatted as shown in Figures and respectively.

S_scsr_cg/cp_scsrwalk/sie

sip-seip_acc, sip-seip_op, sie-seie_acc, sie-seie_op

Bits sip.SEIP and sie.SEIE are the interrupt-pending and interrupt-enable bits for supervisor-level external interrupts. If implemented, SEIP is read-only in sip, and is set and cleared by the execution environment, typically through a platform-specific interrupt controller.

S_scsr_cg/cp_scsrwalk/sip, InterruptsS_cg/cp_trigger_sei

sip-stip_acc, sip-stip_op, sie-stie_acc, sie-stie_op

Bits sip.STIP and sie.STIE are the interrupt-pending and interrupt-enable bits for supervisor-level timer interrupts. If implemented, STIP is read-only in sip. When the Sstc extension is not implemented, STIP is set and cleared by the execution environment. When the Sstc extension is implemented, STIP reflects the timer interrupt signal resulting from stimecmp. The sip.STIP bit, in response to timer interrupts generated by stimecmp, is set by writing stimecmp with a value that is less than or equal to time, and is cleared by writing stimecmp with a value greater than time.

S_scsr_cg/cp_scsrwalk/sip, InterruptsS_cg/cp_trigger_sti

sip-ssip_acc, sip-ssip_op, sie-ssie_acc, sie-ssie_op

Bits sip.SSIP and sie.SSIE are the interrupt-pending and interrupt-enable bits for supervisor-level software interrupts. If implemented, SSIP is writable in sip and may also be set to 1 by a platform-specific interrupt controller.

S_scsr_cg/cp_scsrwalk/sip, InterruptsS_cg/cp_trigger_ssi, InterruptsS_cg/cp_trigger_ssi_sip

sip_unimpl_acc, sie_unimpl_acc

Each standard interrupt type (SEI, STI, SSI, or LCOFI) may not be implemented, in which case the corresponding interrupt-pending and interrupt-enable bits are read-only zeros. All bits in sip and sie are WARL fields. The implemented interrupts may be found by writing one to every bit location in sie, then reading back to see which bit positions hold a one.

S_scsr_cg/cp_scsr_access/{sie, sip}

sip_priority_bit_order, sie_priority_bit_order

Multiple simultaneous interrupts destined for supervisor mode are handled in the following decreasing priority order: SEI, SSI, STI, LCOFI.

InterruptsS_cg/cp_priority_mip

supervisor_timer_scheduling

The implementation must provide a facility for scheduling timer interrupts in terms of the real-time counter, time.

OUT-OF-SCOPE: too vague if handled by software setting STIP. Tested by InterruptsSstc_cg/cp_supervisor_sti when Sstc implemented

sscratch_sz, sscratch_acc, sscratch_mode

The sscratch CSR is an SXLEN-bit read/write register, dedicated for use by the supervisor. Typically, sscratch is used to hold a pointer to the hart-local supervisor context while the hart is executing user code. At the beginning of a trap handler, software normally uses a CSRRW instruction to swap sscratch with an integer register to obtain an initial working register.

S_scsr_cg/cp_scsr_access/sscratch

sepc_sz, sepc_acc, sepc_op, sepc_mode

sepc is an SXLEN-bit read/write CSR formatted as shown in . The low bit of sepc (sepc[0]) is always zero. On implementations that support only IALIGN=32, the two low bits (sepc[1:0]) are always zero.

S_scsr_cg/cp_scsr_access/sepc

sepc_op_mask_ialign32

If an implementation allows IALIGN to be either 16 or 32 (by changing CSR misa, for example), then, whenever IALIGN=32, bit sepc[1] is masked on reads so that it appears to be 0. This masking occurs also for the implicit read by the SRET instruction. Though masked, sepc[1] remains writable when IALIGN=32.

OUT-OF-SCOPE

sepc_acc_invalid_addr

sepc is a WARL register that must be able to hold all valid virtual addresses. It need not be capable of holding all possible invalid addresses. Prior to writing sepc, implementations may convert an invalid address into some other invalid address that sepc is capable of holding.

S_scsr_cg/cp_scsr_access/sepc

sepc_op_trap_write

When a trap is taken into S-mode, sepc is written with the virtual address of the instruction that was interrupted or that encountered the exception. Otherwise, sepc is never written by the implementation, though it may be explicitly written by software.

ExceptionsS_cg/cp_illegal_instruction, InterruptsS_cg/cp_interrupts_s

scause_sz, scause_acc, scause_op

The scause CSR is an SXLEN-bit read-write register formatted as shown in . When a trap is taken into S-mode, scause is written with a code indicating the event that caused the trap. Otherwise, scause is never written by the implementation, though it may be explicitly written by software.

S_scsr_cg/cp_scsr_access/scause, ExceptionsS_cg/cp_illegal_instruction, InterruptsS_cg/cp_interrupts_s

scause-interrupt_sz, scause-interrupt_op

The Interrupt bit in the scause register is set if the trap was caused by an interrupt. The Exception Code field contains a code identifying the last exception or interrupt. lists the possible exception codes for the current supervisor ISAs. The Exception Code is a WLRL field. It is required to hold the values 0–31 (i.e., bits 4–0 must be implemented), but otherwise it is only guaranteed to hold supported exception codes.

S_scause_cg/cp_scause_write_{interrupt, exception}, ExceptionsS_cg/cp_illegal_instruction, InterruptsS_cg/cp_interrupts_s

scause-exception_code_acc

S_scause_cg/cp_scause_write_{interrupt, exception}

scause-exception_code_sz

It is required to hold the values 0–31 (i.e., bits 4–0 must be implemented), but otherwise it is only guaranteed to hold supported exception codes.

S_scause_cg/cp_scause_write_{interrupt, exception}

stval_sz, stval_op, stval_mode

The stval CSR is an SXLEN-bit read-write register formatted as shown in . When a trap is taken into S-mode, stval is written with exception-specific information to assist software in handling the trap. Otherwise, stval is never written by the implementation, though it may be explicitly written by software. The hardware platform will specify which exceptions must set stval informatively, which may unconditionally set it to zero, and which may exhibit either behavior, depending on the underlying event that caused the exception.

S_stval_cg/cp_stval_write, ExceptionsS_cg/cp_illegal_instruction

stval_op_faulting_addr

If stval is written with a nonzero value when a breakpoint, address-misaligned, access-fault, page-fault, or hardware-error exception occurs on an instruction fetch, load, or store, then stval will contain the faulting virtual address.

ExceptionsS_cg/{cp_breakpoint, cp_{load,store,instr}_address_misaligned, cp_{load,store, instr}_access_fault,cp_illegal_instruction

stval_op_breakpoint

On a breakpoint exception raised by an EBREAK or C.EBREAK instruction, stval is written with either zero or the virtual address of the instruction.

ExceptionsS_cg/cp_breakpoint

stval_op_load_store_fault

If stval is written with a nonzero value when a misaligned load or store causes an access-fault, page-fault, or hardware-error exception, then stval will contain the virtual address of the portion of the access that caused the fault.

TODO: write coverpoints for misaligned loads that wrap PMA/PMP/page boundaries to cause faults on upper part of access

stval_faulting_address_variable_instr

If stval is written with a nonzero value when an instruction access-fault, page-fault, or hardware-error exception occurs on a hart with variable-length instructions, then stval will contain the virtual address of the portion of the instruction that caused the fault, while sepc will point to the beginning of the instruction.

OUT-OF-SCOPE variable-length instructions

stval_op_illegal_instr

The stval register can optionally also be used to return the faulting instruction bits on an illegal-instruction exception (sepc points to the faulting instruction in memory). If stval is written with a nonzero value when an illegal-instruction exception occurs, then stval will contain the shortest of:

ExceptionsS_cg/cp_illegal_instruction

stval_op_illegal_instr_format

The value loaded into stval on an illegal-instruction exception is right-justified and all unused upper bits are cleared to zero.

ExceptionsZc_cg/cp_illegal_instruction, SsstrictS_comp_instr_cg/cp_compressed00

stval_op_other_traps

For other traps, stval is set to zero, but a future standard may redefine stval’s setting for other traps.

ExceptionsS_cg/cp_ecall_s, InterruptsS_cg/cp_interrupts_s

stval_acc

stval is a WARL register that must be able to hold all valid virtual addresses and the value 0. It need not be capable of holding all possible invalid addresses. Prior to writing stval, implementations may convert an invalid address into some other invalid address that stval is capable of holding. If the feature to return the faulting instruction bits is implemented, stval must also be able to hold all values less than 2N, where N is the smaller of SXLEN and ILEN.

S_scsr_cg/cp_scsr_access/stval

senvcfg_sz, senvcfg_acc, senvcfg_mode

The senvcfg CSR is an SXLEN-bit read/write register, formatted as shown in , that controls certain characteristics of the U-mode execution environment.

S_scsr_cg/cp_scsr_access/senvcfg

senvcfg-fiom_op

If bit FIOM (Fence of I/O implies Memory) is set to one in senvcfg, FENCE instructions executed in U-mode are modified so the requirement to order accesses to device I/O implies also the requirement to order main memory accesses. details the modified interpretation of FENCE instruction bits PI, PO, SI, and SO in U-mode when FIOM=1.

OUT-OF-SCOPE

senvcfg-fiom_op_atomic

Similarly, for U-mode when FIOM=1, if an atomic instruction that accesses a region ordered as device I/O has its aq and/or rl bit set, then that instruction is ordered as though it accesses both device I/O and memory.

OUT-OF-SCOPE

senvcfg-fiom_sz

If bit FIOM (Fence of I/O implies Memory) is set to one in senvcfg, FENCE instructions executed in U-mode are modified so the requirement to order accesses to device I/O implies also the requirement to order main memory accesses. details the modified interpretation of FENCE instruction bits PI, PO, SI, and SO in U-mode when FIOM=1.

S_scsr_cg/cp_scsr_access/senvcfg

senvcfg-fiom_acc

If satp.MODE is read-only zero (always Bare), the implementation may make FIOM read-only zero.

S_scsr_cg/cp_scsr_access/senvcfg

UDB Parameters: None.

sie_sip_strap_time_constraint is not tested yet. How to handle timing constraints in certification? How to handle interrupts that don’t get evaluated immediately after the macro sets them? The macro could spin until they fire, but needs to know if they should fire (e.g. not blocked by xstatus.xIE).

B.1.3. U User-Mode CSRs and Instructions

These test additional CSRs that exist in user mode, and privileged instructions in user mode.

Table 133. U Coverpoints

Google Sheet Testplan

TODO: Incorporate normative rules now that Sm is fully tagged.

B.1.4. SmF Floating-Point CSRs

These test additional CSRs that exist when floating-point is supported.

Table 134. SmF Coverpoints

Google Sheet Testplan

B.1.5. SmV Vector CSRs and Instructions

These test additional CSRs and vset* instructions that exist when vector is supported.

Table 135. SmV Coverpoints

Google Sheet Testplan

B.1.6. SmVF Vector Floating-Point CSRs

These test additional CSRs that exist when vector floating-point is supported.

Table 136. SmVF Coverpoints

Google Sheet Testplan

B.1.7. UF User-Mode Floating-Point CSRs

These test additional CSR scenarios that exist when floating-point and user mode are supported.

Table 137. UF Coverpoints

Google Sheet Testplan

B.1.8. UV User-Mode Vector CSRs

These test additional CSR scenarios that exist when vector and user mode are supported.

Table 138. UV Coverpoints

Google Sheet Testplan

B.1.9. Zkr Entropy CSR

These test CSRs when the Zkr entropy extension is supported.

Table 139. Zkr Coverpoints

  • reorganize to Zkr section

B.2. Exceptions

Exception tests are organized according to the privilege mode or extension supported. For example, a configuration with Machine, Supervisor, User, and Floating-Point supported should run ExceptionsSm, ExceptionsS, ExceptionsU, and ExceptionsF.

B.2.1. ExceptionsSm Machine-Mode Exceptions

These tests are run on any configuration with machine mode that supports exceptions.

Table 140. ExceptionsSm Coverpoints

Google Sheet Testplan
Table 141. ExceptionsSm Normative Rules
Normative Rule Rule Text Coverpoints

taken_cti_misaligned_exc

An instruction-address-misaligned exception is generated on a taken branch or unconditional jump if the target address is not IALIGN-bit aligned. This exception is reported on the branch or jump instruction, not on the target instruction.

ExceptionsSm_cg/{cp_instr_adr_misaligned_branch, cp_instr_adr_misaligned_jal, cp_instr_adr_misaligned_jalr}

mepc_op

When a trap is taken into M-mode, mepc is written with the virtual address of the instruction that was interrupted or that encountered the exception. Otherwise, mepc is never written by the implementation, though it may be explicitly written by software.

ExceptionsSm/cp_illegal_instruction (etc)

mcause_op

When a trap is taken into M-mode, mcause is written with a code indicating the event that caused the trap. Otherwise, mcause is never written by the implementation, though it may be explicitly written by software.

ExceptionsSm/cp_{instr_adr_misaligned_branch, instr_access_fault, illegal_instruction, breakpoint, load_address_misaligned, load_access_fault, store_address_misaligned, store_access_fault, ecall_m}

mcause_exccode_op

The Exception Code field contains a code identifying the last exception or interrupt.

ExceptionsSm/cp_{instr_adr_misaligned_branch, instr_access_fault, illegal_instruction, breakpoint, load_address_misaligned, load_access_fault, store_address_misaligned, store_access_fault, ecall_m}

mcause_exccode_enc

Interrupt|Exception Code|Description === 1 1 1 1|0 1 2 3|Reserved Supervisor software interrupt Reserved Machine software interrupt¶1 1 1 1|4 5 6 7|Reserved Supervisor timer interrupt Reserved Machine timer interrupt¶1 1 1 1|8 9 10 11|Reserved Supervisor external interrupt Reserved Machine external interrupt¶1 1 1 1|12 13 14-15 ≥16|Reserved Counter-overflow interrupt Reserved Designated for platform use¶0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0|0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20-23 24-31 32-47 48-63 ≥64|Instruction address misaligned Instruction access fault Illegal instruction Breakpoint Load address misaligned Load access fault Store/AMO address misaligned Store/AMO access fault Environment call from U-mode Environment call from S-mode Reserved Environment call from M-mode Instruction page fault Load page fault Reserved Store/AMO page fault Double trap Reserved Software check Hardware error Reserved Designated for custom use Reserved Designated for custom use Reserved ===

ExceptionsSm/cp_{instr_adr_misaligned_branch, instr_access_fault, illegal_instruction, breakpoint, load_address_misaligned, load_access_fault, store_address_misaligned, store_access_fault, ecall_m}

mtvec_mode_enc

Value|Name|Description === 0 1 ≥2|Direct Vectored ---|All traps set pc to BASE. Asynchronous interrupts set pc to BASE+4×cause. Reserved ===

TODO

mtvec_mode_direct_op

When MODE=Direct, all traps into machine mode cause the pc to be set to the address in the BASE field.

TODO

mtvec_mode_vectored_op

When MODE=Vectored, all synchronous exceptions into machine mode cause the pc to be set to the address in the BASE field, whereas interrupts cause the pc to be set to the address in the BASE field plus four times the interrupt cause number.

TODO

trap_def_M-mode

By default, all traps at any privilege level are handled in machine mode

ExceptionsSm/cp_{instr_adr_misaligned_branch, instr_access_fault, illegal_instruction, breakpoint, load_address_misaligned, load_access_fault, store_address_misaligned, store_access_fault, ecall_m}

mcause_exccode_ld_ldrsv

Note that load and load-reserved instructions generate load exceptions

cond_br_no_ia_misaligned_exc_not_taken

No instruction-address-misaligned exception is generated for a conditional branch that is not taken.

ExceptionsSm_cg/cp_instr_adr_misaligned_branch_nottaken

ia_fault_exc_on_target

If an instruction access-fault or instruction page-fault exception occurs on the target of a jump or taken branch, the exception is reported on the target instruction, not on the jump or branch instruction.

ExceptionsSm_cg/cp_instr_access_fault, TODO for page fault

branch_misaligned_taken_exception

The conditional branch instructions will generate an instruction-address-misaligned exception if the target address is not aligned to a four-byte boundary and the branch condition evaluates to true.

ExceptionsSm_cg/cp_instr_adr_misaligned_branch

branch_misaligned_untaken_exception

If the branch condition evaluates to false, the instruction-address-misaligned exception will not be raised.

ExceptionsSm_cg/cp_instr_adr_misaligned_branch_nottaken

jump_misaligned_exception

The JAL and JALR instructions will generate an instruction-address-misaligned exception if the target address is not aligned to a four-byte boundary.

ExceptionsSm_cg/{cp_instr_adr_misaligned_jal, cp_instr_adr_misaligned_jalr}

ldst_no_exc_aligned

loads and stores whose effective addresses are naturally aligned shall not raise an address-misaligned exception.

ExceptionsSm_cg/{cp_load_address_misaligned, cp_store_address_misaligned}

load_exc_x0

Loads with a destination of x0 must still raise any exceptions and cause any other side effects even though the load value is discarded.

TODO

MISALIGNED_LDST_EEI_DEPENDENT_BEHAVIOR

Loads and stores whose effective address is not naturally aligned to the referenced datatype (i.e., the effective address is not divisible by the size of the access in bytes) have behavior dependent on the EEI.

ExceptionsSm_cg/{cp_load_address_misaligned, cp_store_address_misaligned}

MISALIGNED_LDST_FULLY_HW_SUPPORTED

misaligned loads and stores can be handled in hardware

ExceptionsSm_cg/{cp_load_address_misaligned, cp_store_address_misaligned}

MISALIGNED_LDST_INVISIBLE_TRAP

via an invisible trap into the execution environment implementation

ExceptionsSm_cg/{cp_load_address_misaligned, cp_store_address_misaligned}

MISALIGNED_LDST_HW_OR_INVISIBLE_TRAP_FUNC_OF_ADDR

combination of hardware and invisible trap depending on address.

ExceptionsSm_cg/{cp_load_address_misaligned, cp_store_address_misaligned}

MISALIGNED_LDST_FULLY_HW_SUPPORTED_OR_VISIBLE_TRAP

loads and stores that are not naturally aligned may either complete execution successfully or raise an exception.

ExceptionsSm_cg/{cp_load_address_misaligned, cp_store_address_misaligned}

MISALIGNED_LDST_CONTAINED_OR_FATAL_TRAP

When an EEI does not guarantee misaligned loads and stores are handled invisibly, the EEI must define if exceptions caused by address misalignment result in a contained trap (allowing software running inside the execution environment to handle the trap) or a fatal trap (terminating execution).

ExceptionsSm_cg/{cp_load_address_misaligned, cp_store_address_misaligned}

ldst_addr_misaligned_or_access_fault_exc

ExceptionsSm_cg/{cp_load_address_misaligned, cp_store_address_misaligned}

ldst_atomicity_for_aligned

naturally aligned loads and stores are guaranteed to execute atomically

ExceptionsSm_cg/{cp_load_address_misaligned, cp_store_address_misaligned}

ecall_op

The ECALL instruction is used to make a service request to the execution environment. The ECALL instruction is used to make a request to the supporting execution environment. When executed in U-mode, S-mode, or M-mode, it generates an environment-call-from-U-mode exception, environment-call-from-S-mode exception, or environment-call-from-M-mode exception, respectively, and performs no other operation.

ExceptionsSm_cg/cp_ecall_m

ebreak_op

The EBREAK instruction is used to return control to a debugging environment. The EBREAK instruction is used by debuggers to cause control to be transferred back to a debugging environment. Unless overridden by an external debug environment, EBREAK raises a breakpoint exception and performs no other operation.

ExceptionsSm_cg/cp_breakpoint_m

mepc_op

When a trap is taken into M-mode, mepc is written with the virtual address of the instruction that was interrupted or that encountered the exception. Otherwise, mepc is never written by the implementation, though it may be explicitly written by software.

ExceptionsSm/{cp_instr_adr_misaligned_branch, cp_instr_access_fault, cp_illegal_instruction, cp_breakpoint, cp_load_address_misaligned, cp_load_access_fault, cp_store_address_misaligned, cp_store_access_fault, cp_ecall_m}

mcause_op

When a trap is taken into M-mode, mcause is written with a code indicating the event that caused the trap. Otherwise, mcause is never written by the implementation, though it may be explicitly written by software.

ExceptionsSm/cp_{instr_adr_misaligned_branch, instr_access_fault, illegal_instruction, breakpoint, load_address_misaligned, load_access_fault, store_address_misaligned, store_access_fault, ecall_m}

mcause_exccode_op

The Exception Code field contains a code identifying the last exception or interrupt.

ExceptionsSm/cp_{instr_adr_misaligned_branch, instr_access_fault, illegal_instruction, breakpoint, load_address_misaligned, load_access_fault, store_address_misaligned, store_access_fault, ecall_m}

mcause_exccode_enc

Interrupt|Exception Code|Description === 1 1 1 1|0 1 2 3|Reserved Supervisor software interrupt Reserved Machine software interrupt¶1 1 1 1|4 5 6 7|Reserved Supervisor timer interrupt Reserved Machine timer interrupt¶1 1 1 1|8 9 10 11|Reserved Supervisor external interrupt Reserved Machine external interrupt¶1 1 1 1|12 13 14-15 ≥16|Reserved Counter-overflow interrupt Reserved Designated for platform use¶0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0|0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20-23 24-31 32-47 48-63 ≥64|Instruction address misaligned Instruction access fault Illegal instruction Breakpoint Load address misaligned Load access fault Store/AMO address misaligned Store/AMO access fault Environment call from U-mode Environment call from S-mode Reserved Environment call from M-mode Instruction page fault Load page fault Reserved Store/AMO page fault Double trap Reserved Software check Hardware error Reserved Designated for custom use Reserved Designated for custom use Reserved ===

ExceptionsSm/cp_{instr_adr_misaligned_branch, instr_access_fault, illegal_instruction, breakpoint, load_address_misaligned, load_access_fault, store_address_misaligned, store_access_fault, ecall_m}

mtvec_mode_enc

Value|Name|Description === 0 1 ≥2|Direct Vectored ---|All traps set pc to BASE. Asynchronous interrupts set pc to BASE+4×cause. Reserved ===

TODO show mtvec does not affect synchronous exceptions

mtvec_mode_direct_op

When MODE=Direct, all traps into machine mode cause the pc to be set to the address in the BASE field.

TODO

mtvec_mode_vectored_op

When MODE=Vectored, all synchronous exceptions into machine mode cause the pc to be set to the address in the BASE field, whereas interrupts cause the pc to be set to the address in the BASE field plus four times the interrupt cause number.

TODO

trap_def_M-mode

By default, all traps at any privilege level are handled in machine mode

ExceptionsSm/cp_{instr_adr_misaligned_branch, instr_access_fault, illegal_instruction, breakpoint, load_address_misaligned, load_access_fault, store_address_misaligned, store_access_fault, ecall_m}

mcause_exccode_pri

If an instruction may raise multiple synchronous exceptions, the decreasing priority order of [norm:exc_priority] indicates which exception is taken and reported in mcause. Load/store/AMO address-misaligned exceptions may have either higher or lower priority than load/store/AMO page-fault and access-fault exceptions.

ExceptionsSm_cg/{cp_misaligned_priority_load, cp_misaligned_priority_store}

exc_priority

Priority|Exc.Code|Description === Highest|3|Instruction address breakpoint¶|12, 1|During instruction address translation: First encountered page fault or access fault¶|1|With physical address for instruction: Instruction access fault¶|2 0 8,9,11 3 3|Illegal instruction Instruction address misaligned Environment call Environment break Load/store/AMO address breakpoint¶|4,6|Optionally: Load/store/AMO address misaligned¶|13, 15, 5, 7|During address translation for an explicit memory access: First encountered page fault or access fault¶|5,7|With physical address for an explicit memory access: Load/store/AMO access fault¶Lowest|4,6|If not higher priority: Load/store/AMO address misaligned ===

ExceptionsSm_cg/{cp_misaligned_priority_load, cp_misaligned_priority_store, cp_misaligned_priority_fetch}
Table 142. ExceptionsSm UDB Parameters
Parameter Description Coverpoint Effect

MISALIGNED_LDST

Does the implementation perform non-atomic misaligned loads and stores to main memory (does not affect misaligned support to device memory)? If not, the implementation always throws a misaligned exception.

cp_{load_address_misaligned, store_address_misaligned, cp_misaligned_priority_load, cp_misaligned_priority_store}

When true, misaligned loads and stores do not cause exceptions

MISALIGNED_LDST_EXCEPTION_PRIORITY

The relative priority of a load/store/AMO exception vs. load/store/AMO page-fault or access-fault exceptions.

May be one of:

[separator="!"] !=== ! low ! Misaligned load/store/AMO exceptions are always lower priority than load/store/AMO page-fault and access-fault exceptions. ! high ! Misaligned load/store/AMO exceptions are always higher priority than load/store/AMO page-fault and access-fault exceptions. !===

MISALIGNED_LDST_EXCEPTION_PRIORITY cannot be "high" when MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE is non-zero, since the atomicity of an access cannot be determined in that case until after address translation.

cp_misaligned_priority_load, cp_misaligned_priority_store

When true, misaligned loads and stores do not cause exceptions

MTVAL_WIDTH

The number of implemented bits in the mtval CSR. This is the CSR that may be written when a trap is taken into M-mode with exception-specific information to assist software in handling the trap (e.g., address associated with exception).

Must be greater than or equal to max(PHYS_ADDR_WIDTH, VA_SIZE)

TODO

MTVEC_ACCESS

Options:

ro:: mtvec is read-only.

rw:: mtvec is read-write, but may not accept all values.

all exception coverpoints

If 'ro', tests cannot set mtvec and generate a trap signature

MTVEC_BASE_ALIGNMENT_DIRECT

Minimum alignment of the base pointer. Because mtvec excludes the two least-significant bits of the base, the minimum alignment cannot be less than 4.

all exception coverpoints

DUT config/rvmodel_macros.h must set RVMODEL_MTVEC_ALIGN if alignment > 64 bytes

MTVEC_ILLEGAL_WRITE_BEHAVIOR

Options:

retain:: When either mtvec.MODE or mtvec.BASE is illegal, mtvec will retain its current value

custom:: When either mtvec.MODE or mtvec.BASE is illegal, mtvec will obtain an unpredictable value

Other values may be added over time once other common behaviors are identified.

all exception coverpoints

If mtvec cannot be written with trap handler, tests will not operate

REPORT_ENCODING_IN_MTVAL_ON_ILLEGAL_INSTRUCTION

Options:

* true: mtval is written with the encoding of an instruction causing an IllegalInstruction exception * false: mtval is written with 0 when an instruction causes an IllegalInstruction exception.

cp_illegal_instruction

Affects value written to mtval

REPORT_VA_IN_MTVAL_ON_BREAKPOINT

Options:

* true: mtval is written with the virtual PC of an EBREAK instruction (same information as mepc). * false: mtval is written with 0 on an EBREAK instruction.

Regardless, mtval is always written with a virtual PC when an external breakpoint is generated

cp_breakpoint

Affects value written to mtval

REPORT_VA_IN_MTVAL_ON_INSTRUCTION_ACCESS_FAULT

Options:

* true: mtval is written with the virtual address of a fetch causing the access fault * false: mtval is written with 0 when a fetch causes an access fault

cp_instr_access_fault

Affects value written to mtval

REPORT_VA_IN_MTVAL_ON_INSTRUCTION_MISALIGNED

Options:

* true: mtval is written with the virtual address of a trapping misaligned fetch * false: mtval is written with 0 when a misaligned fetch traps

cp_instr_adr_misaligned_branch, cp_instr_misaligned_jal, cp_instr_misaligned_jalr

Affects value written to mtval

REPORT_VA_IN_MTVAL_ON_LOAD_ACCESS_FAULT

Options:

* true: mtval is written with the virtual address of a load causing the access fault * false: mtval is written with 0 when a load causes an access fault

cp_load_access_fault

Affects value written to mtval

REPORT_VA_IN_MTVAL_ON_LOAD_MISALIGNED

Options:

* true: mtval is written with the virtual address of a trapping misaligned load. * false: mtval is written with 0 when a misaligned load traps.

cp_load_address_misaligned

Affects value written to mtval

REPORT_VA_IN_MTVAL_ON_STORE_AMO_ACCESS_FAULT

Options:

* true: mtval is written with the virtual address of a store or AMO causing the access fault * false: mtval is written with 0 when a store or AMO causes an access fault

cp_store_access_fault

Affects value written to mtval

REPORT_VA_IN_MTVAL_ON_STORE_AMO_MISALIGNED

Options:

* true: mtval is written with the virtual address of a trapping misaligned store or AMO. * false: mtval is written with 0 when a misaligned store or AMO traps.

cp_store_address_misaligned

Affects value written to mtval

TRAP_ON_EBREAK

The spec states that implementations may handle EBREAKs transparently without raising a trap, in which case the EEI must provide a builtin.

cp_breakpoint

TODO

TRAP_ON_ECALL_FROM_M

The spec states that implementations may handle ECALLs transparently without raising a trap, in which case the EEI must provide a builtin.

cp_ecall_m

TODO

B.2.2. ExceptionsS Supervisor-Mode Exceptions

These additional exception tests are run on configurations with supervisor mode.

Table 143. ExceptionsS Coverpoints

Google Sheet Testplan
Table 144. ExceptionsS Normative Rules
Normative Rule Rule Text Coverpoints

medeleg_enc

medeleg has a bit position allocated for every synchronous exception shown in [norm:mcause_exccode_enc_img], with the index of the bit position equal to the value returned in the mcause register

ExceptionsS_cg/cp_medeleg_msu

trap_del_S-mode_op

When a trap is delegated to S-mode the scause register is written with the trap cause; the sepc register is written with the virtual address of the instruction that took the trap; the stval register is written with an exception-specific datum; the SPP field of mstatus is written with the active privilege mode at the time of the trap; the SPIE field of mstatus is written with the value of the SIE field at the time of the trap; and the SIE field of mstatus is cleared.

ExceptionsS_cg/cp_medeleg_msu

trap_never_trans_lower

Traps never transition from a more-privileged mode to a less-privileged mode. For example, if M-mode has delegated illegal-instruction exceptions to S-mode, and M-mode software later executes an illegal instruction, the trap is taken in M-mode, rather than being delegated to S-mode.

ExceptionsS_cg/cp_medeleg_msu

trap_horiz

traps may be taken horizontally. Using the same example, if M-mode has delegated illegal-instruction exceptions to S-mode, and S-mode software later executes an illegal instruction, the trap is taken in S-mode.

ExceptionsS_cg/cp_medeleg_msu

trap_del_intr_priv_lvl

Delegated interrupts result in the interrupt being masked at the delegator privilege level. For example, if the supervisor timer interrupt (STI) is delegated to S-mode by setting mideleg[5], STIs will not be taken when executing in M-mode. By contrast, if mideleg[5] is clear, STIs can be taken in any mode and regardless of current mode will transfer control to M-mode.

TODO

mstatus_xpie_trap_op, mstatus_xie_trap_op, mstatus_xpp_trap_op

When a trap is taken from privilege mode y into privilege mode x, xPIE is set to the value of xIE; xIE is set to 0; and xPP is set to y.

sstatus-spp_sz, sstatus-spp_acc, sstatus-spp_op

The SPP bit indicates the privilege level at which a hart was executing before entering supervisor mode. When a trap is taken, SPP is set to 0 if the trap originated from user mode, or 1 otherwise. When an SRET instruction (see ) is executed to return from the trap handler, the privilege level is set to user mode if the SPP bit is 0, or supervisor mode if the SPP bit is 1; SPP is then set to 0.

UDB Parameters: None.

B.2.3. ExceptionsU User-Mode Exceptions

These additional exception tests are run on configurations with user mode.

Table 145. ExceptionsU Coverpoints

Google Sheet Testplan
Table 146. ExceptionsU Normative Rules
Normative Rule Rule Text Coverpoints

mstatus_xpie_trap_op, mstatus_xie_trap_op, mstatus_xpp_trap_op

When a trap is taken from privilege mode y into privilege mode x, xPIE is set to the value of xIE; xIE is set to 0; and xPP is set to y.

UDB Parameters: None.

B.2.4. ExceptionsF Floating-Point Exceptions

These additional exception tests are run on configurations with floating-point (at least the F extension).

Table 147. ExceptionsF Coverpoints

Google Sheet Testplan

B.2.5. ExceptionsVx Vector Integer Exceptions

These additional exception tests are run on configurations with vector (V extension or subsets thereof that rely on mstatus.VS) related to vector integer instructions.

Table 148. ExceptionsVx Coverpoints

Google Sheet Testplan

B.2.6. ExceptionsVf Vector Floating-Point Exceptions

These additional exception tests are run on configurations with vector (V extension or subsets thereof that rely on mstatus.VS) related to vector floating-point instructions.

Table 149. ExceptionsVf Coverpoints

Google Sheet Testplan

B.2.7. ExceptionsVls Vector Load/Store Exceptions

These additional exception tests are run on configurations with vector (V extension or subsets thereof that rely on mstatus.VS) related to vector load/store instructions.

Table 150. ExceptionsVls Coverpoints
Google Sheet Testplan

B.2.8. ExceptionsZalrsc Atomic LR/SC Exceptions

Table 151. ExceptionsZalrsc Coverpoints

Google Sheet Testplan

B.2.9. ExceptionsZaamo Atomic Memory Operation Exceptions

Table 152. ExceptionsZaamo Coverpoints

Google Sheet Testplan
ExceptionsZaamo also covers Zama16b.

B.2.10. ExceptionsZc Compressed Instruction Exceptions

These additional exception tests are run on configurations with compressed instructions (C, Zca, Zcb, etc.). They attempt to test all compressed loads and stores, but may throw an illegal instruction fault on compressed subword load/store if Zcb is not supported.

Table 153. ExceptionsZc Coverpoints

Google Sheet Testplan
Table 154. ExceptionsZc Normative Rules
Normative Rule Rule Text Coverpoints

Zca_no_misaligned

With the addition of the C extension, no instructions can raise instruction-address-misaligned exceptions.

Exceptions/{cp_instr_adr_misaligned_branch, cp_instr_adr_misaligned_jal, cp_instr_adr_misaligned_jalr}

Zca_illegal

A 16-bit instruction with all bits zero is permanently reserved as an illegal instruction.

ExceptionsZca_cg/cp_illegal_instruction

c-ebreak_op

Debuggers can use the C.EBREAK instruction, which expands to ebreak, to cause control to be transferred back to the debugging environment. C.EBREAK shares the opcode with the C.ADD instruction, but with rd and rs2 both zero, thus can also use the CR format.

ExceptionsZca_cg/cp_breakpoint

c-ebreak

C.JALR is valid only when rs1≠x0; the code point with rs1=x0 corresponds to the C.EBREAK instruction.

ExceptionsZca_cg/cp_breakpoint

Zca_align16

The C extension allows 16-bit instructions to be freely intermixed with 32-bit instructions, with the latter now able to start on any 16-bit boundary, i.e., IALIGN=16.

ExceptionsSm_cg/cp_instr_access_fault

misa-c_set

MISA.C is set if the following extensions are selected: Zca and not F Zca, Zcf and F (but not D) is specified (RV32 only) Zca, Zcf and Zcd if D is specified (RV32 only) this configuration excludes Zcmp, Zcmt Zca, Zcd if D is specified (RV64 only) this configuration excludes Zcmp, Zcmt

Sm_mcsr_cg/cp_mcsr_access/misa

branch_misaligned_c_no_exception

Instruction-address-misaligned exceptions are not possible on machines with IALIGN=16, e.g., those with the compressed instruction-set extension, C.

ExceptionsSm_cg/cp_instr_adr_misaligned_branch

jump_misaligned_c_no_exception

Instruction-address-misaligned exceptions are not possible on machines with IALIGN=16, e.g., those with the compressed instruction-set extension, C.

ExceptionsSm_cg/{cp_instr_adr_misaligned_jal, cp_instr_adr_misaligned_jalr}

UDB Parameters: None.

B.2.11. ExceptionsZicboS Supervisor-Mode CBO Exceptions

Table 155. ExceptionsZicboS Coverpoints

Google Sheet Testplan

B.2.12. ExceptionsZicboU User-Mode CBO Exceptions

Table 156. ExceptionsZicboU Coverpoints

Google Sheet Testplan

B.2.13. ExceptionsSv Virtual Memory Exceptions

Table 157. ExceptionsSv Coverpoints

Google Sheet Testplan

B.2.14. ExceptionsSvZalrsc Virtual Memory LR/SC Exceptions

Table 158. ExceptionsSvZalrsc Coverpoints

Google Sheet Testplan

B.2.15. ExceptionsSvZaamo Virtual Memory AMO Exceptions

Table 159. ExceptionsSvZaamo Coverpoints

Google Sheet Testplan

B.3. Interrupts

Interrupt tests are organized according to the privilege mode or extension supported.

B.3.1. InterruptsSm Machine-Mode Interrupts

These tests are run on any configuration with machine mode that supports interrupts.

Table 160. InterruptsSm Coverpoints

Google Sheet Testplan
Table 161. InterruptsSm Normative Rules
Normative Rule Rule Text Coverpoints

mepc_op

When a trap is taken into M-mode, mepc is written with the virtual address of the instruction that was interrupted or that encountered the exception. Otherwise, mepc is never written by the implementation, though it may be explicitly written by software.

InterruptsSm/cp_priority

mcause_op

When a trap is taken into M-mode, mcause is written with a code indicating the event that caused the trap. Otherwise, mcause is never written by the implementation, though it may be explicitly written by software.

InterruptsSm/cp_priority

mcause_intr_op

The Interrupt bit in the mcause register is set if the trap was caused by an interrupt.

InterruptsSm/cp_priority

mcause_exccode_op

The Exception Code field contains a code identifying the last exception or interrupt.

InterruptsSm/cp_priority

mcause_exccode_enc

Interrupt|Exception Code|Description === 1 1 1 1|0 1 2 3|Reserved Supervisor software interrupt Reserved Machine software interrupt¶1 1 1 1|4 5 6 7|Reserved Supervisor timer interrupt Reserved Machine timer interrupt¶1 1 1 1|8 9 10 11|Reserved Supervisor external interrupt Reserved Machine external interrupt¶1 1 1 1|12 13 14-15 ≥16|Reserved Counter-overflow interrupt Reserved Designated for platform use¶0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0|0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20-23 24-31 32-47 48-63 ≥64|Instruction address misaligned Instruction access fault Illegal instruction Breakpoint Load address misaligned Load access fault Store/AMO address misaligned Store/AMO access fault Environment call from U-mode Environment call from S-mode Reserved Environment call from M-mode Instruction page fault Load page fault Reserved Store/AMO page fault Double trap Reserved Software check Hardware error Reserved Designated for custom use Reserved Designated for custom use Reserved ===

InterruptsSm/cp_priority

trap_def_M-mode

By default, all traps at any privilege level are handled in machine mode

InterruptsSm/cp_priority

mtvec_mode_enc

Value|Name|Description === 0 1 ≥2|Direct Vectored ---|All traps set pc to BASE. Asynchronous interrupts set pc to BASE+4×cause. Reserved ===

InterruptsSm_cg/cp_vectored

mtvec_mode_direct_op

When MODE=Direct, all traps into machine mode cause the pc to be set to the address in the BASE field.

InterruptsSm_cg/cp_vectored

mtvec_mode_vectored_op

When MODE=Vectored, all synchronous exceptions into machine mode cause the pc to be set to the address in the BASE field, whereas interrupts cause the pc to be set to the address in the BASE field plus four times the interrupt cause number.

InterruptsSm_cg/cp_vectored

mstatus_mie_op

Global interrupt-enable bits, MIE and SIE, are provided for M-mode and S-mode respectively. When a hart is executing in privilege mode x, interrupts are globally enabled when xIE=1 and globally disabled when xIE=0.

InterruptsSm_cg/cp_interupts

mstatus_xpie_op, mstatus_xpp_op

each privilege mode x that can respond to interrupts has a two-level stack of interrupt-enable bits and privilege modes. xPIE holds the value of the interrupt-enable bit active prior to the trap, and xPP holds the previous privilege mode.

InterruptsSm_cg/cp_interupts

mstatus_xpie_trap_op, mstatus_xie_trap_op, mstatus_xpp_trap_op

When a trap is taken from privilege mode y into privilege mode x, xPIE is set to the value of xIE; xIE is set to 0; and xPP is set to y.

InterruptsSm_cg/cp_interupts

mstatus_tw_warl

InterruptsSm_cg/cp_wfi

mip_enc

Interrupt cause number i (as reported in CSR mcause, [mcause]) corresponds with bit i in both mip and mie. Bits 15:0 are allocated to standard interrupt causes only, while bits 16 and above are designated for platform use.

InterruptsSm/cp_priority

mie_enc

Interrupt cause number i (as reported in CSR mcause, [mcause]) corresponds with bit i in both mip and mie. Bits 15:0 are allocated to standard interrupt causes only, while bits 16 and above are designated for platform use.

InterruptsSm/cp_priority

mip_std_enc

The standard portions (bits 15:0) of the mip and mie registers are formatted as shown in [norm:mip_std_enc_img] and [norm:mie_std_enc_img] respectively.

InterruptsSm/cp_priority

mie_std_enc

The standard portions (bits 15:0) of the mip and mie registers are formatted as shown in [norm:mip_std_enc_img] and [norm:mie_std_enc_img] respectively.

InterruptsSm/cp_priority

mip_bits_rdonly_op

If interrupt i can become pending but bit i in mip is read-only, the implementation must provide some other mechanism for clearing the pending interrupt.

InterruptsSm/cp_interrupts

mip_meip_op, mie_meie_op

Bits mip.MEIP and mie.MEIE are the interrupt-pending and interrupt-enable bits for machine-level external interrupts.

InterruptsSm/cp_interrupts

mip_meip_rdonly

MEIP is read-only in mip, and is set and cleared by a platform-specific interrupt controller.

Sm_cg/cp_mcsr_access/mip, InterruptsSm/trigger_mei

mip_mtip_op, mie_mtie_op

Bits mip.MTIP and mie.MTIE are the interrupt-pending and interrupt-enable bits for machine timer interrupts.

InterruptsSm/cp_interrupts

mip_mtip_rdonly

MTIP is read-only in the mip register, and is cleared by writing to the memory-mapped machine-mode timer compare register.

Sm_cg/cp_mcsr_access/mip, InterruptsSm/trigger_mti

mip_msip_op, mie_msie_op

Bits mip.MSIP and mie.MSIE are the interrupt-pending and interrupt-enable bits for machine-level software interrupts.

InterruptsSm/cp_interrupts

mip_msip_rdonly

MSIP is read-only in mip, and is written by accesses to memory-mapped control registers, which are used to provide machine-level interprocessor interrupts.

Sm_cg/cp_mcsr_access/mip, InterruptsSm/trigger_msi

msip_sz, msip_acc

A hart’s memory-mapped msip register is a 32-bit read/write register

InterruptsSm/trigger_msi

msip_enc

bits 31—​1 read as zero and bit 0 contains the MSIP bit.

InterruptsSm/cp_trigger_msi, TODO read and record MSIP reg

msip_update_max_time

InterruptsSm/cp_trigger_msi

intr_mip_mie_op

An interrupt i will trap to M-mode (causing the privilege mode to change to M-mode) if all of the following are true: (a) either the current privilege mode is M and the MIE bit in the mstatus register is set, or the current privilege mode has less privilege than M-mode; (b) bit i is set in both mip and mie; and (c) if register mideleg exists, bit i is not set in mideleg.

InterruptsSm/cp_interrupts

intr_mip_mie_bounded_time

An interrupt i will trap to M-mode (causing the privilege mode to change to M-mode) if all of the following are true: (a) either the current privilege mode is M and the MIE bit in the mstatus register is set, or the current privilege mode has less privilege than M-mode; (b) bit i is set in both mip and mie; and (c) if register mideleg exists, bit i is not set in mideleg. These conditions for an interrupt trap to occur must be evaluated in a bounded amount of time from when an interrupt becomes, or ceases to be, pending in mip,

InterruptsSm/cp_interrupts

intr_mip_mie_xret_csrwr

An interrupt i will trap to M-mode (causing the privilege mode to change to M-mode) if all of the following are true: (a) either the current privilege mode is M and the MIE bit in the mstatus register is set, or the current privilege mode has less privilege than M-mode; (b) bit i is set in both mip and mie; and (c) if register mideleg exists, bit i is not set in mideleg. be evaluated immediately following the execution of an xRET instruction or an explicit write to a CSR on which these interrupt trap conditions expressly depend (including mip, mie, mstatus, and mideleg).

InterruptsSm/cp_interrupts

intr_M-mode_pri

Multiple simultaneous interrupts destined for M-mode are handled in the following decreasing priority order: MEI, MSI, MTI, SEI, SSI, STI, LCOFI.

InterruptsSm/cp_priority
Table 162. InterruptsSm UDB Parameters
Parameter Description Coverpoint Effect

MTVEC_ACCESS

Options:

ro:: mtvec is read-only.

rw:: mtvec is read-write, but may not accept all values.

all exception coverpoints

If 'ro', tests cannot set mtvec and generate a trap signature

MTVEC_BASE_ALIGNMENT_DIRECT

Minimum alignment of the base pointer. Because mtvec excludes the two least-significant bits of the base, the minimum alignment cannot be less than 4.

all exception coverpoints

DUT config/rvmodel_macros.h must set RVMODEL_MTVEC_ALIGN if alignment > 64 bytes

MTVEC_BASE_ALIGNMENT_VECTORED

Because mtvec excludes the two least-significant bits of the base, the minimum alignment cannot be less than 4.

all

DUT config/rvmodel_macros.h must set RVMODEL_MTVEC_ALIGN if alignment > 64 bytes

MTVEC_ILLEGAL_WRITE_BEHAVIOR

Options:

retain:: When either mtvec.MODE or mtvec.BASE is illegal, mtvec will retain its current value

custom:: When either mtvec.MODE or mtvec.BASE is illegal, mtvec will obtain an unpredictable value

Other values may be added over time once other common behaviors are identified.

all

If mtvec cannot be written with trap handler, tests will not operate

MTVEC_MODES

Options:

0:: Direct; All traps set pc to mtvec.BASE 1:: Vectored; Asynchronous interrupts set pc to mtvec.BASE + 4 x cause.

If only one mode is given, mtvec.MODE is assumed to be read-only with that value. Otherwise, mtvec.MODE is read-write.

TODO

If direct or vectored are not supported, tests relying on those modes will not operate TODO should not be run

TODO: coverpoints will need to ignore bins with mie.msie nonzero: # If a system has only one hart, or if a platform standard supports the delivery # of machine-level interprocessor interrupts through external interrupts (MEI) # instead, then mip.MSIP and mie.MSIE may both be read-only zeros. - name: mie_msie_maybe_rdonly0 TODO: mip.MSIP update time # When the memory-mapped msip register changes, it is guaranteed to be reflected # in mip.MSIP eventually, but not necessarily immediately. - name: msip_update_max_time

B.3.2. InterruptsS Supervisor-Mode Interrupts

These tests are run on any configuration with supervisor mode that supports interrupts. Note that they include tests in other modes, such as interrupts from user mode delegated to supervisor mode.

Table 163. InterruptsS Coverpoints

Google Sheet Testplan
Table 164. InterruptsS Normative Rules
Normative Rule Rule Text Coverpoints

trap_del_S-mode_op

When a trap is delegated to S-mode the scause register is written with the trap cause; the sepc register is written with the virtual address of the instruction that took the trap; the stval register is written with an exception-specific datum; the SPP field of mstatus is written with the active privilege mode at the time of the trap; the SPIE field of mstatus is written with the value of the SIE field at the time of the trap; and the SIE field of mstatus is cleared.

InterruptsS_cg/cp_priority_mideleg_s

mideleg_op

InterruptsS_cg/cp_trigger_{mti/msi/mei/sti/ssi_mip/ssi_sip/sei_sei_seip}

mideleg_enc

mideleg holds trap delegation bits for individual interrupts, with the layout of bits matching those in the mip register

InterruptsS_cg/cp_trigger_{mti/msi/mei/sti/ssi_mip/ssi_sip/sei_sei_seip}

mstatus_sie_op

Global interrupt-enable bits, MIE and SIE, are provided for M-mode and S-mode respectively. When a hart is executing in privilege mode x, interrupts are globally enabled when xIE=1 and globally disabled when xIE=0.

mstatus_xie_intr_en_dis

Interrupts for lower-privilege modes, w<x, are always globally disabled regardless of the setting of any global wIE bit for the lower-privilege mode. Interrupts for higher-privilege modes, y>x, are always globally enabled regardless of the setting of the global yIE bit for the higher-privilege mode.

mstatus_xpie_op, mstatus_xpp_op

each privilege mode x that can respond to interrupts has a two-level stack of interrupt-enable bits and privilege modes. xPIE holds the value of the interrupt-enable bit active prior to the trap, and xPP holds the previous privilege mode.

mstatus_xpie_trap_op, mstatus_xie_trap_op, mstatus_xpp_trap_op

When a trap is taken from privilege mode y into privilege mode x, xPIE is set to the value of xIE; xIE is set to 0; and xPP is set to y.

mstatus_tw_op

When TW=0, the WFI instruction may execute in modes less privileged than M when not prevented for some other reason. When TW=1, then if WFI is executed in any less-privileged mode, and it does not complete within an implementation-specific, bounded time limit, the WFI instruction causes an illegal-instruction exception.

mip_enc

Interrupt cause number i (as reported in CSR mcause, [mcause]) corresponds with bit i in both mip and mie. Bits 15:0 are allocated to standard interrupt causes only, while bits 16 and above are designated for platform use.

mie_enc

Interrupt cause number i (as reported in CSR mcause, [mcause]) corresponds with bit i in both mip and mie. Bits 15:0 are allocated to standard interrupt causes only, while bits 16 and above are designated for platform use.

mip_std_enc

The standard portions (bits 15:0) of the mip and mie registers are formatted as shown in [norm:mip_std_enc_img] and [norm:mie_std_enc_img] respectively.

mie_std_enc

The standard portions (bits 15:0) of the mip and mie registers are formatted as shown in [norm:mip_std_enc_img] and [norm:mie_std_enc_img] respectively.

mip_bits_wr_op

When bit i in mip is writable, a pending interrupt i can be cleared by writing 0 to this bit.

InterruptsS/{cp_trigger_ssi_mip, cp_trigger_ssi_sip, cp_trigger_sei_seip}

intr_mip_mie_op

An interrupt i will trap to M-mode (causing the privilege mode to change to M-mode) if all of the following are true: (a) either the current privilege mode is M and the MIE bit in the mstatus register is set, or the current privilege mode has less privilege than M-mode; (b) bit i is set in both mip and mie; and (c) if register mideleg exists, bit i is not set in mideleg.

intr_mip_mie_xret_csrwr

An interrupt i will trap to M-mode (causing the privilege mode to change to M-mode) if all of the following are true: (a) either the current privilege mode is M and the MIE bit in the mstatus register is set, or the current privilege mode has less privilege than M-mode; (b) bit i is set in both mip and mie; and (c) if register mideleg exists, bit i is not set in mideleg. be evaluated immediately following the execution of an xRET instruction or an explicit write to a CSR on which these interrupt trap conditions expressly depend (including mip, mie, mstatus, and mideleg).

intr_M-mode_highest_pri

Interrupts to M-mode take priority over any interrupts to lower privilege modes.

intr_sei_op

Supervisor-level external interrupts are made pending based on the logical-OR of the software-writable SEIP bit and the signal from the external interrupt controller.

intr_M-mode_pri

Multiple simultaneous interrupts destined for M-mode are handled in the following decreasing priority order: MEI, MSI, MTI, SEI, SSI, STI, LCOFI.

trap_never_trans_lower

Traps never transition from a more-privileged mode to a less-privileged mode. For example, if M-mode has delegated illegal-instruction exceptions to S-mode, and M-mode software later executes an illegal instruction, the trap is taken in M-mode, rather than being delegated to S-mode.

TODO

trap_horiz

traps may be taken horizontally. Using the same example, if M-mode has delegated illegal-instruction exceptions to S-mode, and S-mode software later executes an illegal instruction, the trap is taken in S-mode.

TODO

trap_del_intr_priv_lvl

Delegated interrupts result in the interrupt being masked at the delegator privilege level. For example, if the supervisor timer interrupt (STI) is delegated to S-mode by setting mideleg[5], STIs will not be taken when executing in M-mode. By contrast, if mideleg[5] is clear, STIs can be taken in any mode and regardless of current mode will transfer control to M-mode.

TODO

mstatus_tw_umode_op

When S-mode is implemented, then executing WFI in U-mode causes an illegal-instruction exception, regardless of the value of the TW bit, unless the instruction completes within an implementation-specific, bounded time limit.

mip_seip_op, mie_seie_op

If supervisor mode is implemented, bits mip.SEIP and mie.SEIE are the interrupt-pending and interrupt-enable bits for supervisor-level external interrupts.

* some will need to move to S priv

mip_seip_acc

SEIP is writable in mip

mip_seip_rdcsr

When mip is read with a CSR instruction, the value of the SEIP bit returned in the rd destination register is the logical-OR of the software-writable bit and the interrupt signal from the interrupt controller

mip_seip_wrcsr

the signal from the interrupt controller is not used to calculate the value written to SEIP. Only the software-writable SEIP bit participates in the read-modify-write sequence of a CSRRS or CSRRC instruction.

mip_stip_no-stimecmp_acc

If the stimecmp register is not implemented, STIP is writable in mip

mip_stip_no-stimecmp_op

If supervisor mode is implemented, its mip.STIP and mie.STIE are the interrupt-pending and interrupt-enable bits for supervisor-level timer interrupts. If the stimecmp register is not implemented, STIP is writable in mip may be written by M-mode software to deliver timer interrupts to S-mode.

mip_stip_stimecmp_acc

If the stimecmp (supervisor-mode timer compare) register is implemented, STIP is read-only in mip

mip_stip_stimecmp_op

If supervisor mode is implemented, its mip.STIP and mie.STIE are the interrupt-pending and interrupt-enable bits for supervisor-level timer interrupts. If the stimecmp (supervisor-mode timer compare) register is implemented, STIP is read-only in mip reflects the supervisor-level timer interrupt signal resulting from stimecmp.

mip_stip_stimecmp_clr

This timer interrupt signal is cleared by writing stimecmp with a value greater than the current time value.

mip_stie_op

If supervisor mode is implemented, its mip.STIP and mie.STIE are the interrupt-pending and interrupt-enable bits for supervisor-level timer interrupts.

mip_ssip_acc

SSIP is writable in mip

mip_ssip_op, mie_ssie_op

If supervisor mode is implemented, bits mip.SSIP and mie.SSIE are the interrupt-pending and interrupt-enable bits for supervisor-level software interrupts.

mip_ssip_intr_ctrl

SSIP is writable in mip may also be set to 1 by a platform-specific interrupt controller.
Table 165. InterruptsS UDB Parameters
Parameter Description Coverpoint Effect

STVEC_MODE_DIRECT

Whether or not stvec.MODE supports Direct (0).

TODO

TODO

STVEC_MODE_VECTORED

Whether or not stvec.MODE supports Vectored (1).

TODO

TODO

B.3.3. InterruptsU User-Mode Interrupts

These tests are run on any configuration with user mode that supports interrupts.

Table 166. InterruptsU Coverpoints

Google Sheet Testplan
Table 167. InterruptsU Normative Rules
Normative Rule Rule Text Coverpoints

mstatus_tw_time_limit

mstatus_tw_always_illegal

mstatus_xpie_op, mstatus_xpp_op

each privilege mode x that can respond to interrupts has a two-level stack of interrupt-enable bits and privilege modes. xPIE holds the value of the interrupt-enable bit active prior to the trap, and xPP holds the previous privilege mode.

mstatus_xpie_trap_op, mstatus_xie_trap_op, mstatus_xpp_trap_op

When a trap is taken from privilege mode y into privilege mode x, xPIE is set to the value of xIE; xIE is set to 0; and xPP is set to y.

intr_mip_mie_xret_csrwr

An interrupt i will trap to M-mode (causing the privilege mode to change to M-mode) if all of the following are true: (a) either the current privilege mode is M and the MIE bit in the mstatus register is set, or the current privilege mode has less privilege than M-mode; (b) bit i is set in both mip and mie; and (c) if register mideleg exists, bit i is not set in mideleg. be evaluated immediately following the execution of an xRET instruction or an explicit write to a CSR on which these interrupt trap conditions expressly depend (including mip, mie, mstatus, and mideleg).

mstatus_tw_op

When TW=0, the WFI instruction may execute in modes less privileged than M when not prevented for some other reason. When TW=1, then if WFI is executed in any less-privileged mode, and it does not complete within an implementation-specific, bounded time limit, the WFI instruction causes an illegal-instruction exception.

UDB Parameters: None.

B.3.4. InterruptsSstc Supervisor Timer Compare Interrupts

These tests are run when the Sstc supervisor timer compare extension is supported.

Table 168. InterruptsSstc Coverpoints

Google Sheet Testplan
Table 169. InterruptsSstc Normative Rules
Normative Rule Rule Text Coverpoints

menvcfg-stce

InterruptsSstc_cg/cp_{supervisor/user}_stce. See also SstcH

mcounteren_tm_clr

when the TM bit in the mcounteren register is clear, attempts to access the stimecmp or vstimecmp register while executing in a mode less privileged than M will cause an illegal-instruction exception.

InterruptsSstc_cg/cp_{supervisor,user}_tm, see also SstcH

mcounteren_tm_set

When this bit is set, access to the stimecmp or vstimecmp register is permitted in S-mode if implemented, and access to the vstimecmp register (via stimecmp) is permitted in VS-mode if implemented and not otherwise prevented by the TM bit in hcounteren.

InterruptsSstc_cg/cp_{supervisor,user}_tm, see also SstcH

stimecmp-stimecmph_sz_acc

The stimecmp CSR is a 64-bit register and has 64-bit precision on all RV32 and RV64 systems. In RV32 only, accesses to the stimecmp CSR access the low 32 bits, while accesses to the stimecmph CSR access the high 32 bits of stimecmp.

mip_stip_op, sip_stip_op

A supervisor timer interrupt becomes pending, as reflected in the STIP bit in the mip and sip registers whenever time contains a value greater than or equal to stimecmp, treating the values as unsigned integers. If the result of this comparison changes, it is guaranteed to be reflected in STIP eventually, but not necessarily immediately. The interrupt remains posted until stimecmp becomes greater than time, typically as a result of writing stimecmp. The interrupt will be taken based on the standard interrupt enable and delegation rules.

UDB Parameters: None.

TODO: beef up testing stimecmp values, behavior near wraparound

B.4. Zicntr

These privileged tests exercise counters and HPMs reads (time, cycle, instret, hpmcounter[31:3]) from lower privilege modes, as controlled by mcounteren, etc.. Note that the Zicntr and Zihpm unprivileged tests exercise access to these counters from M-mode and the Sm tests exercise access to mcycle, minstret, mhpmcounter, etc. from M-mode.

B.4.1. ZicntrS Supervisor-Mode Counter Reads

Table 170. ZicntrS Coverpoints

Google Sheet Testplan

B.4.2. ZicntrU User-Mode Counter Reads

Table 171. ZicntrU Coverpoints

Google Sheet Testplan

B.5. Endian

B.5.1. EndianSm Machine-Mode Endianness

Table 172. EndianSm Coverpoints

Google Sheet Testplan

B.5.2. EndianS Supervisor-Mode Endianness

Table 173. EndianS Coverpoints

Google Sheet Testplan

B.5.3. EndianU User-Mode Endianness

Table 174. EndianU Coverpoints

Google Sheet Testplan

B.5.4. EndianZaamo Endianness for AMOs

Table 175. EndianZaamo Coverpoints

Google Sheet Testplan

B.5.5. EndianZalrsc Endianness for LR/SC

Table 176. EndianZalrsc Coverpoints

Google Sheet Testplan

B.5.6. EndianF Endianness for Floats

Table 177. EndianF Coverpoints

Google Sheet Testplan

B.5.7. EndianZca Endianness for Compressed Instructions

Table 178. EndianZca Coverpoints

Google Sheet Testplan

B.6. Ssstrict

The Ssstrict extension indicates that executing unimplemented instructions or accessing unimplemented CSR in the standard or reserved encoding spaces raises an illegal instruction exception.

No non-conforming extensions are present. Attempts to execute unimplemented opcodes or access unimplemented CSRs in the standard or reserved encoding spaces raises an illegal instruction exception that results in a contained trap to the supervisor-mode trap handler.
— https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc[RVA23 profile Ssstrict definition]

B.6.1. SsstrictSm

RISC-V does not have a ratified equivalent of Ssstrict for machine mode, but this optional test suite checks the behavior of unimplemented instructions and CSRs from machine mode. It runs the same tests as SsstrictS but from machine mode.

B.6.2. SsstrictS

Attempt to issue all flavors of 32-bit instructions in the standard and reserved spaces and all 16-bit compressed instructions. Also attempt to access all CSRs in the standard and reserved spaces. Expect illegal instruction trap for unimplemented instructions and CSRs, matching reference model.

According to the RVA23 profile spec, the illegal instruction should be cause a trap to the supervisor trap handler. However, delegation is the business of the firmware, not the hardware. These tests only check that a trap occurs and matches the reference model.

SsstrictS Coverpoints

Google Sheet Testplan

Table 179. SsstrictS Normative Rules
Normative Rule Rule Text Coverpoints

slliw_imm5_rsv

SLLIW, SRLIW, and SRAIW encodings with imm[5] ≠ 0 are reserved.

SsstrictS_instr_cg/cp_IWshift

c-addi16sp_rsv

C.ADDI16SP is valid only when nzimm≠0; the code point with nzimm=0 is reserved.

SsstrictS_comp_instr_cg/cp_compressed01

c-addi4spn_rsv

C.ADDI4SPN is valid only when nzuimm≠0; the code points with nzuimm=0 are reserved.

SsstrictS_comp_instr_cg/cp_compressed00

c-addiw_rsv

C.ADDIW is valid only when rd≠x0; the code points with rd=x0 are reserved.

SsstrictS_comp_instr_cg/cp_compressed01

c-jr_rsv

C.JR is valid only when rs1≠x0; the code point with rs1=x0 is reserved.

SsstrictS_comp_instr_cg/cp_compressed10

c-ldsp_rsv

C.LDSP is valid only when rd≠x0; the code points with rd=x0 are reserved.

SsstrictS_comp_instr_cg/cp_compressed10

c-lui_rsv

C.LUI is valid only when rd≠x2, and when the immediate is not equal to zero. The code points with imm=0 are reserved. The code points with rd=x2 and imm≠0 correspond to the C.ADDI16SP instruction.

SsstrictS_comp_instr_cg/cp_compressed01

c-lwsp_rsv

C.LWSP is valid only when rd≠x0; the code points with rd=x0 are reserved.

SsstrictS_comp_instr_cg/cp_compressed10

cm-mvsa01_res

For the encoding to be legal r1s' != r2s'.

SsstrictS_comp_instr_cg/cp_compressed10

roundingmode_rsv

The behavior of floating-point instructions that depend on rounding mode when executed with a reserved rounding mode is reserved, including both static reserved rounding modes (101-110) and dynamic reserved rounding modes (101-111). Some instructions, including widening conversions, have the rm field but are nevertheless mathematically unaffected by the rounding mode; software should set their rm field to RNE (000) but implementations must treat the rm field as usual (in particular, with regard to decoding legal vs. reserved encodings).

SsstrictS_instr_cg/cp_Ftype, ExceptionsF_cg/cp_badfrm

fcvtmod-w-d_rsv

SsstrictS_instr_cg/cp_cvtmodwdfrm

bseti_rv32i_shamt_rsv

SsstrictS_instr_cg/cp_Itype

bclri_rv32i_shamt_rsv

SsstrictS_instr_cg/cp_Itype

binvi_rv32i_shamt_rsv

SsstrictS_instr_cg/cp_Itype

bexti_rv32i_shamt_rsv

SsstrictS_instr_cg/cp_Itype

diff-rv32e-rv32i

RV32E and RV64E use the same instruction-set encoding as RV32I and RV64I respectively, except that only registers x0-x15 are provided. All encodings specifying the other registers x16-x31 are reserved.

{SsstrictS_cg,SsstricM_cg}/{cp_upperreg}

UDB Parameters: None.

B.6.3. SsstrictV

Test that all behaviors called out as "reserved" in the vector specification cause an illegal instruction fault. Required when Ssstrict and V are both present.

SsstrictV Coverpoints

Google Sheet Testplan

Table 180. SsstrictV Normative Rules
Normative Rule Rule Text Coverpoints

EMUL_NFIELDS_rsv

The EMUL setting must be such that EMUL * NFIELDS ≤ 8, otherwise the instruction encoding is reserved.

TODO

EMUL_offgroup_rsv

Using other than the lowest-numbered vector register to specify a vector register group is a reserved encoding.

TODO

EMUL_rsv

The largest vector register group used by an instruction can not be greater than 8 vector registers (i.e., EMUL≤8), and if a vector instruction would require greater than 8 vector registers in a group, the instruction encoding is reserved. For example, a widening operation that produces a widened vector register group result when LMUL=8 is reserved as this would imply a result EMUL=16.

TODO

V_fp_EEW_IEEE_nsupported_rsv

If the EEW of a vector floating-point operand does not correspond to a supported IEEE floating-point type, the instruction encoding is reserved.

TODO

V_fp_eew_rsv

Vector instructions where any floating-point vector operand’s EEW is not a supported floating-point type width (which includes when FLEN < SEW) are reserved.

TODO

V_inv_frm_rsv

Use of the frm field when it contains an invalid rounding mode by any vector floating-point instruction—​even those that do not depend on the rounding mode, or when vl=0, or when vstart ≥ vl—​is reserved.

TODO

egs_ge_vlmax_rsv

Vector instructions with EGS > VLMAX are reserved.

TODO

egs_vl_rsv

When an operand is a vector of element groups, the vl setting must correspond to an integer multiple of the element group size, with other values of vl reserved.

TODO

vadc_unmasked_rsv

Encodings corresponding to the unmasked versions (vm=1) are reserved.

TODO

vadc_vd_v0_rsv

For vadc and vsbc, the instruction encoding is reserved if the destination vector register is v0.

TODO

vcompress_masked_rsv

The equivalent masked instruction (vm=0) is reserved.

TODO

vector_ls_EEW_rsv

If the implementation does not support the EEW of the offset elements, the instruction is reserved.

TODO

vector_ls_EMUL_offgroup_rsv

The vector register groups must have legal register specifiers for the selected EMUL, otherwise the instruction encoding is reserved.

TODO

vector_ls_EMUL_rsv

If the EMUL would be out of range (EMUL>8 or EMUL<1/8), the instruction encoding is reserved.

TODO

vector_ls_ins_rsv

Vector load/store encodings for unsupported EEW widths are reserved.

TODO

vector_ls_mew_rsv

The mew bit (inst[28]) when set is expected to be used to encode expanded memory sizes of 128 bits and above, but these encodings are currently reserved.

TODO

vector_ls_seg_indexed_vreg_rsv

For vector indexed segment loads, the destination vector register groups cannot overlap the source vector register group (specified by vs2), else the instruction encoding is reserved.

TODO

vector_ls_seg_rsv

If the vector register numbers accessed by the segment load or store would increment past 31, then the instruction encoding is reserved.

TODO

vector_ls_seg_wholereg_nf_rsv

Only NFIELDS values of 1, 2, 4, 8 are supported, with other values reserved.

TODO

vfmv-s-f_masked_rsv

The encodings corresponding to the masked versions (vm=0) of vfmv.f.s and vfmv.s.f are reserved.

TODO

vfmv_vs2_nv0_rsv

The instruction must have the vs2 field set to v0, with all other values for vs2 reserved.

TODO

vid_vs2_nv0_rsv

The vs2 field of the instruction must be set to v0, otherwise the encoding is reserved.

TODO

vmasklogical_masked_rsv

so there are no inactive elements, and the encodings with vm=0 are reserved.

TODO

vmv-nr-r_nreg_rsv

The value of NREG must be 1, 2, 4, or 8, and values of simm[4:0] other than 0, 1, 3, and 7 are reserved.

TODO

vmv-nr-r_unaligned_rsv

encodings with other vector register numbers are reserved.

TODO

vmv-s-x_masked_rsv

The encodings corresponding to the masked versions (vm=0) of vmv.x.s and vmv.s.x are reserved.

TODO

vmv-x-s_masked_rsv

The encodings corresponding to the masked versions (vm=0) of vmv.x.s and vmv.s.x are reserved.

TODO

vmv_vs2_nv0_rsv

The first operand specifier (vs2) must contain v0, and any other vector register number in vs2 is reserved.

TODO

vreg_offgroup_LMUL2_rsv

Instructions specifying an LMUL=2 vector register group with an odd-numbered vector register are reserved.

TODO

vreg_offgroup_LMUL4_rsv

instructions specifying an LMUL=4 vector register group using vector register numbers that are not multiples of four are reserved.

TODO

vreg_offgroup_LMUL8_rsv

instructions specifying an LMUL=8 vector register group using register numbers that are not multiples of eight are reserved.

TODO

vreg_overlap_rsv

Any instruction encoding that violates the overlap constraints is reserved.

TODO

vreg_source_EEW_rsv

A vector register cannot be used to provide source operands with more than one EEW for a single instruction. A mask register source is considered to have EEW=1 for this constraint. An encoding that would result in the same vector register being read with two or more different EEWs, including when the vector register appears at different positions within two or more vector register groups, is reserved.

TODO

vreg_vmask_rsv

The destination vector register group for a masked vector instruction cannot overlap the source mask register (v0), unless the destination vector register is being written with a mask value (e.g., compares) or the scalar result of a reduction. These instruction encodings are reserved.

TODO

vsbc_unmasked_rsv

Encodings corresponding to the unmasked versions (vm=1) are reserved.

TODO

vsbc_vd_v0_rsv

For vadc and vsbc, the instruction encoding is reserved if the destination vector register is v0.

TODO

vsext_ill_eew_emul_rsv

If the source EEW is not a supported width, or source EMUL would be below the minimum legal LMUL, the instruction encoding is reserved.

TODO

vstart_val_rsv

The use of vstart values greater than the largest element index for the current vtype setting is reserved.

TODO

vtype-lmul_fval_rsv

The use of vtype encodings with LMUL < SEWMIN/ELEN is reserved, but implementations can set vill if they do not support these configurations.

TODO

vtype-vsew_rsv

While it is anticipated the larger vsew[2:0] encodings (100-111) will be used to encode larger SEW, the encodings are formally reserved at this point.

TODO

vtype_vset_rsv

Use of the instructions with a new SEW/LMUL ratio that would result in a change of VLMAX is reserved. Use of the instructions is also reserved if vill was 1 beforehand.

TODO

vzext_ill_eew_emul_rsv

If the source EEW is not a supported width, or source EMUL would be below the minimum legal LMUL, the instruction encoding is reserved.

TODO

vclmul_sewn64_rsv

SEW is any value other than 64

TODO

vclmulh_sewn64_rsv

SEW is any value other than 64

TODO

veccrypto_sew_rsv

Some Vector Crypto instructions are only defined for a specific SEW. In such a case all other SEW values are reserved.

TODO

veccrypto_vl_rsv

Instructions that violate the vl or vstart requirements are reserved.

TODO

veccrypto_vstart_rsv

Instructions that violate the vl or vstart requirements are reserved.

TODO

vghsh-vv_sewn32_rsv

SEW is any value other than 32

TODO

vgmul-vv_sewn32_rsv

SEW is any value other than 32

TODO

vsha2ch-vv_Zvknha_sewn32_rsv

zvknha: SEW is any value other than 32

TODO

vsha2ch-vv_Zvknhb_sewn32or64_rsv

zvknhb: SEW is any value other than 32 or 64

TODO

vsha2ch-vv_vdoverlapvs1vs2_rsv

The vd register group overlaps with either vs1 or vs2

TODO

vsha2cl-vv_Zvknha_sewn32_rsv

zvknha: SEW is any value other than 32

TODO

vsha2cl-vv_Zvknhb_sewn32or64_rsv

zvknhb: SEW is any value other than 32 or 64

TODO

vsha2cl-vv_vdoverlapvs1vs2_rsv

The vd register group overlaps with either vs1 or vs2

TODO

vsha2ms-vv_Zvknha_sewn32_rsv

zvknha: SEW is any value other than 32

TODO

vsha2ms-vv_Zvknhb_sewn32or64_rsv

zvknhb: SEW is any value other than 32 or 64

TODO

vsha2ms-vv_vdoverlapvs1vs2_rsv

The vd register group overlaps with either vs1 or vs2

TODO

vsm3c-vi_sewn32_rsv

SEW is any value other than 32

TODO

vsm3c-vi_vdoverlapvs2_rsv

The vd register group overlaps with the vs2 register group

TODO

vsm3me-vv_sewn32_rsv

SEW is any value other than 32

TODO

vsm3me-vv_vdoverlapvs2_rsv

The vd register group overlaps with the vs2 register group.

TODO

vsm4k-vi_sewn32_rsv

SEW is any value other than 32

TODO

vsm4r-vs_vdoverlapvs2_rsv

Only for the .vs form: the vd register group overlaps the vs2 register

TODO

vsm4r_sewn32_rsv

SEW is any value other than 32

TODO

UDB Parameters: None.

B.7. PMP

B.7.1. PMPSm

Table 181. PMPSm Coverpoints

Google Sheet Testplan

B.7.2. PMPS

Table 182. PMPS Coverpoints

Google Sheet Testplan

B.7.3. PMPU

Table 183. PMPU Coverpoints

Google Sheet Testplan

B.7.4. PMPF

Table 184. PMPF Coverpoints

Google Sheet Testplan

B.7.5. PMPZca

Table 185. PMPZca Coverpoints

Google Sheet Testplan

B.7.6. PMPZicbo

Table 186. PMPZicbo Coverpoints

Google Sheet Testplan

B.7.7. PMPZaamo

Table 187. PMPZaamo Coverpoints

Google Sheet Testplan

B.7.8. PMPZalrsc

Table 188. PMPZalrsc Coverpoints

Google Sheet Testplan

B.8. Sv* Virtual Memory

B.8.1. Svbare Virtual Memory Off

B.8.2. Sv

Svbare Coverpoints

  • config file determines whether to run SV32/39/48/57

Table 189. Sv Coverpoints

Google Sheet Testplan
Table 190. Sv Normative Rules
Normative Rule Rule Text Coverpoints

sstatus-mxr_sz, sstatus-mxr_acc, sstatus-mxr_op

The MXR (Make eXecutable Readable) bit modifies the privilege with which loads access virtual memory. When MXR=0, only loads from pages marked readable (R=1 in ) will succeed. When MXR=1, loads from pages marked either readable or executable (R=1 or X=1) will succeed. MXR has no effect when page-based virtual memory is not in effect.

sstatus-sum_sz, sstatus-sum_acc, sstatus-sum_op

The SUM (permit Supervisor User Memory access) bit modifies the privilege with which S-mode loads and stores access virtual memory. When SUM=0, S-mode memory accesses to pages that are accessible by U-mode (U=1 in ) will fault. When SUM=1, these accesses are permitted. SUM has no effect when page-based virtual memory is not in effect, nor when executing in U-mode. Note that S-mode can never execute instructions from user pages, regardless of the state of SUM.

satp_sz, satp_acc, satp_op, satp_mode

The satp CSR is an SXLEN-bit read/write register, formatted as shown in for SXLEN=32 and for SXLEN=64, which controls supervisor-mode address translation and protection. This register holds the physical page number (PPN) of the root page table, i.e., its supervisor physical address divided by 4 KiB; an address space identifier (ASID), which facilitates address-translation fences on a per-address-space basis; and the MODE field, which selects the current address-translation scheme. Further details on the access to this register are described in .

Sv_satp_cg/access_m_s, TODO rest of the bits

satp-mode_sz, satp-mode_acc, satp-mode_op

shows the encodings of the MODE field when SXLEN=32 and SXLEN=64. When MODE=Bare, supervisor virtual addresses are equal to supervisor physical addresses, and there is no additional memory protection beyond the physical memory protection scheme described in . To select MODE=Bare, software must write zero to the remaining fields of satp (bits 30–0 when SXLEN=32, or bits 59–0 when SXLEN=64). Attempting to select MODE=Bare with a nonzero pattern in the remaining fields has an UNSPECIFIED effect on the value that the remaining fields assume and an UNSPECIFIED effect on address translation and protection behavior.

satp-mode_sxlen32

When SXLEN=32, the only other valid setting for MODE is Sv32, a paged virtual-memory scheme described in .

Sv_satp_cg/satp_bare, SV_PA_VA_cg/VA_d_mode

satp-mode_sxlen64

When SXLEN=64, three paged virtual-memory schemes are defined: Sv39, Sv48, and Sv57, described in , , and , respectively. One additional scheme, Sv64, will be defined in a later version of this specification. The remaining MODE settings are reserved for future use and may define different interpretations of the other fields in satp.

Sv_satp_cg/satp_bare, SV_PA_VA_cg/VA_d_mode

satp-mode_op_unsupported

Implementations are not required to support all MODE settings, and if satp is written with an unsupported MODE, the entire write has no effect; no fields in satp are modified.

satp-asidlen

satp_op_active

The satp CSR is considered active when the effective privilege mode is S-mode or U-mode. Executions of the address-translation algorithm may only begin using a given value of satp when satp is active.

satp_op_sfence-vma

Note that writing satp does not imply any ordering constraints between page-table updates and subsequent address translations, nor does it imply any invalidation of address-translation caches. If the new address space’s page tables have been modified, or if an ASID is reused, it may be necessary to execute an SFENCE.VMA instruction (see ) after, or in some cases before, writing satp.

sfence-vma_op

The supervisor memory-management fence instruction SFENCE.VMA is used to synchronize updates to in-memory memory-management data structures with current execution. Instruction execution causes implicit reads and writes to these data structures; however, these implicit references are ordinarily not ordered with respect to explicit loads and stores. Executing an SFENCE.VMA instruction guarantees that any previous stores already visible to the current RISC-V hart are ordered before certain implicit references by subsequent instructions in that hart to the memory-management data structures. The specific set of operations ordered by SFENCE.VMA is determined by rs1 and rs2, as described below. SFENCE.VMA is also used to invalidate entries in the address-translation cache associated with a hart (see ). Further details on the behavior of this instruction are described in and .

sfence-vma_ordering

Executing an SFENCE.VMA instruction guarantees that any previous stores already visible to the current RISC-V hart are ordered before certain implicit references by subsequent instructions in that hart to the memory-management data structures. The specific set of operations ordered by SFENCE.VMA is determined by rs1 and rs2, as described below.

sfence-vma_invalidation

SFENCE.VMA is also used to invalidate entries in the address-translation cache associated with a hart (see [sv32algorithm]).

sfence-vma_all_asid_va

If rs1=x0 and rs2=x0, the fence orders all reads and writes made to any level of the page tables, for all address spaces. The fence also invalidates all address-translation cache entries, for all address spaces.

sfence-vma_asid_only

If rs1=x0 and rs2≠x0, the fence orders all reads and writes made to any level of the page tables, but only for the address space identified by integer register rs2. Accesses to global mappings (see [translation]) are not ordered. The fence also invalidates all address-translation cache entries matching the address space identified by integer register rs2, except for entries containing global mappings.

sfence-vma_va_all_asid

If rs1≠x0 and rs2=x0, the fence orders only reads and writes made to leaf page table entries corresponding to the virtual address in rs1, for all address spaces. The fence also invalidates all address-translation cache entries that contain leaf page table entries corresponding to the virtual address in rs1, for all address spaces.

sfence-vma_va_asid

If rs1≠x0 and rs2≠x0, the fence orders only reads and writes made to leaf page table entries corresponding to the virtual address in rs1, for the address space identified by integer register rs2. Accesses to global mappings are not ordered. The fence also invalidates all address-translation cache entries that contain leaf page table entries corresponding to the virtual address in rs1 and that match the address space identified by integer register rs2, except for entries containing global mappings.

sfence-vma_invalid_va

If the value held in rs1 is not a valid virtual address, then the SFENCE.VMA instruction has no effect. No exception is raised in this case.

sfence-vma_rs2_bits

When rs2≠x0, bits SXLEN-1:ASIDMAX of the value held in rs2 are reserved for future standard use. Until their use is defined by a standard extension, they should be zeroed by software and ignored by current implementations. Furthermore, if ASIDLEN<ASIDMAX, the implementation shall ignore bits ASIDMAX-1:ASIDLEN of the value held in rs2.

sfence-vma_ordering_semantics

An implicit read of the memory-management data structures may return any translation for an address that was valid at any time since the most recent SFENCE.VMA that subsumes that address. The ordering implied by SFENCE.VMA does not place implicit reads and writes to the memory-management data structures into the global memory order in a way that interacts cleanly with the standard RVWMO ordering rules. In particular, even though an SFENCE.VMA orders prior explicit accesses before subsequent implicit accesses, and those implicit accesses are ordered before their associated explicit accesses, SFENCE.VMA does not necessarily place prior explicit accesses before subsequent explicit accesses in the global memory order. These implicit loads also need not otherwise obey normal program order semantics with respect to prior loads or stores to the same address.

sfence-vma_implicit_access

Implementations must only perform implicit reads of the translation data structures pointed to by the current contents of the satp register or a subsequent valid (V=1) translation data structure entry, and must only raise exceptions for implicit accesses that are generated as a result of instruction execution, not those that are performed speculatively.

sfence-vma-sum-mxr_effect

Changes to the sstatus fields SUM and MXR take effect immediately, without the need to execute an SFENCE.VMA instruction.

sfence-vma-mode_effect

Changing satp.MODE from Bare to other modes and vice versa also takes effect immediately, without the need to execute an SFENCE.VMA instruction.

sfence-vma-asid_effect

Likewise, changes to satp.ASID take effect immediately.

asid_hart_private

If a hart employs an address-translation cache, that cache must appear to be private to that hart. In particular, the meaning of an ASID is local to a hart; software may choose to use the same ASID to refer to different address spaces on different harts.

satp-mode_roz_sfence_illegal

fetch_page_fault_no_x

Attempting to fetch an instruction from a page that does not have execute permissions raises a fetch page-fault exception.

load_page_fault_no_r

Attempting to execute a load, load-reserved, or cache-block management instruction whose effective address lies within a page without read permissions raises a load page-fault exception.

store_page_fault_no_w

Attempting to execute a store, store-conditional, AMO, or cache-block zero instruction instruction whose effective address lies within a page without write permissions raises a store page-fault exception.

Sv39_sxlen

simple paged virtual-memory system for SXLEN=64

Sv39_va_sz

supports 39-bit virtual address spaces

Sv39_va_signext

must have bits 63–39 all equal to bit 38, or else a page-fault exception will occur

Sv39_vpn_sz

27-bit VPN

satp-ppn_sv39_sz

44-bit PPN

Sv39_levels

three-level page table

Sv39_page_offset_sz

12-bit page offset is untranslated

Sv39_pte_count

29 page table entries (PTEs)

Sv39_pte_sz

eight bytes each

Sv39_pt_sz

exactly the size of a page

Sv39_pt_align

must always be aligned to a page boundary

Sv39_pte_svnapot_rsv

If Svnapot is not implemented, bit 63 remains reserved and must be zeroed by software for forward compatibility, or else a page-fault exception is raised

Sv39_pte_svpbmt_rsv

If Svpbmt is not implemented, bits 62-61 remain reserved and must be zeroed by software for forward compatibility, or else a page-fault exception is raised

Sv39_pte_future_rsv

must be zeroed by software for forward compatibility. If any of these bits are set, a page-fault exception is raised

Sv39_leaf_any_level

Any level of PTE may be a leaf PTE

Sv39_page_sizes

2 MiB megapages and 1 GiB gigapages

Sv39_superpage_align

must be virtually and physically aligned to a boundary equal to its size

Sv39_superpage_align_fault

A page-fault exception is raised if the physical address is insufficiently aligned

Sv39_LEVELS

LEVELS equals 3

Sv39_PTESIZE

PTESIZE equals 8

Sv48_sxlen

riscv.github.io/riscv-isa-manual/snapshot/privileged/index.html#norm%3ASv48_sxlen

Sv48_va_sz

48-bit virtual address spaces

Sv48_requires_Sv39

Implementations that support Sv48 must also support Sv39

Sv48_va_signext

must have bits 63–48 all equal to bit 47, or else a page-fault exception will occur

Sv48_vpn_sz

36-bit VPN

satp-ppn_sv48_sz

44-bit PPN

Sv48_levels

four-level page table

Sv48_page_offset_sz

12-bit page offset is untranslated

Sv48_leaf_any_level

Any level of PTE may be a leaf PTE

Sv48_page_sizes

2 MiB megapages, 1 GiB gigapages, and 512 GiB terapages

Sv48_superpage_align

must be virtually and physically aligned to a boundary equal to its size

Sv48_superpage_align_fault

A page-fault exception is raised if the physical address is insufficiently aligned

Sv48_LEVELS

LEVELS equals 4

Sv48_PTESIZE

PTESIZE equals 8

Sv57_sxlen

RV64 systems

Sv57_va_sz

57-bit virtual address spaces

Sv57_requires_Sv48

Implementations that support Sv57 must also support Sv48

Sv57_va_signext

must have bits 63–57 all equal to bit 56, or else a page-fault exception will occur

Sv57_vpn_sz

45-bit VPN

satp-ppn_sv57_sz

44-bit PPN

Sv57_levels

five-level page table

Sv57_page_offset_sz

12-bit page offset is untranslated

Sv57_leaf_any_level

Any level of PTE may be a leaf PTE

Sv57_page_sizes

2 MiB megapages, 1 GiB gigapages, 512 GiB terapages, and 256 TiB petapages

Sv57_superpage_align

must be virtually and physically aligned to a boundary equal to its size

Sv57_superpage_align_fault

A page-fault exception is raised if the physical address is insufficiently aligned

Sv57_LEVELS

LEVELS equals 5

Sv57_PTESIZE

PTESIZE equals 8

stval_op_faulting_addr

If stval is written with a nonzero value when a breakpoint, address-misaligned, access-fault, page-fault, or hardware-error exception occurs on an instruction fetch, load, or store, then stval will contain the faulting virtual address.

TODO: page faults

UDB Parameters: None.

UDB Parameters:

  • REPORT_VA_IN_{MTVAL/STVAL}ON_{INSTRUCTION/LOAD/STORE_AMO}PAGE_FAULT affects result in {MTVAL,STVAL} during page-fault exceptions, such as coverpoints TODO

  • TODO other coverpoints at least SATP_MODE_BARE, TRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY

B.8.3. SvPMP VirtMem + PMP

Table 191. SvPMP Coverpoints

Google Sheet Testplan

B.8.4. SvZicbo VirtMem + CBOM/CBOZ

  • config file determines whether to run cbom/cboz/both

Table 192. SvZicbo Coverpoints

Google Sheet Testplan

B.8.5. SvPMPZicbo VirtMem + PMP + CBOM/CBOZ

  • config file determines whether to run cbom/cboz/both

Table 193. SvPMPZicbo Coverpoints

Google Sheet Testplan

B.8.6. Svinval Memory Management Unit Table Invalidation

The Svinval extension defines instructions to update memory management tables for virtual memory and optionally for PMP. Their effect is system-dependent, so these tests simply check that the instructions run.

Table 194. Svinval Coverpoints

Google Sheet Testplan

B.8.7. Svade A/D Bit Page Fault Exception

Table 195. Svade Coverpoints

Google Sheet Testplan

B.8.8. Svadu A/D Bit Hardware Update

Table 196. Svadu Coverpoints

Google Sheet Testplan

B.8.9. Svadu A/D Bit Hardware Update + PMP

Table 197. SvaduPMP Coverpoints

Google Sheet Testplan

B.8.10. Svpbmt Page-Based Memory Types

Table 198. Svpbmt Coverpoints

Google Sheet Testplan

B.8.11. Svnapot Naturally-Aligned Power-of-Two Page Sizes

Table 199. Svnapot Coverpoints

Google Sheet Testplan

B.9. H Hypervisor

The Hypervisor Extension adds an H coverage file containing new Hypervisor instructions, and additional coverage files related to exceptions, interrupts, endian, and virtual memory.

B.9.1. H Hypervisor CSRs and Instructions

Table 200. H Coverpoints

Google Sheet Testplan

B.9.2. ExceptionsH Hypervisor Exceptions

Table 201. ExceptionsH Coverpoints

Google Sheet Testplan

B.9.3. ExceptionsHV Hypervisor Vector Exceptions

Table 202. ExceptionsHV Coverpoints

Google Sheet Testplan

B.9.4. InterruptsH Hypervisor Interrupts

Table 203. InterruptsH Coverpoints

Google Sheet Testplan

B.9.5. HV Hypervisor Vector CSRs

Table 204. HV Coverpoints

*[Google Sheet Testplan]

B.9.6. EndianH Hypervisor Endianness

Table 205. EndianH Coverpoints

Google Sheet Testplan

B.9.7. ZicntrH Hypervisor Counters

Table 206. ZicntrH Coverpoints

Google Sheet Testplan

ZicntrH exercises hcounteren for all 32 counters, so no separate ZihpmH suite is needed.

B.9.8. PMPH Hypervisor Physical Memory Protection

Table 207. PMPH Coverpoints

Google Sheet Testplan

B.9.9. SvH Hypervisor 2-Stage Virtual Memory

Table 208. SvH Coverpoints

Google Sheet Testplan

B.9.10. SvHZicbo Hypervisor VirtMem + Cache Block Operations

Table 209. SvHZicbo Coverpoints

Google Sheet Testplan

B.9.11. Shcounterenw Writable Counter Enables

Table 210. Shcounterenw Coverpoints

Google Sheet Testplan

B.9.12. Shvsatpa Virtual Memory Modes Supported

Table 211. Shvsatpa Coverpoints

Google Sheet Testplan

B.9.13. Shgatpa Virtual Memory x4 Modes Supported

Table 212. Shgatpa Coverpoints

Google Sheet Testplan

B.9.14. Shvstvecd VS-Mode Direct Vectors

Table 213. Shvstvecd Coverpoints

Google Sheet Testplan

B.9.15. Shvstvala VS-Mode Trap Address

Table 214. Shvstvala Coverpoints

Google Sheet Testplan

B.9.16. Shtvala HS-Mode Trap Address

Table 215. Shtvala Coverpoints

Google Sheet Testplan

B.9.17. Shlcofideleg Hypervisor Counter Overflow Delegation

Table 216. Shlcofideleg Coverpoints

Google Sheet Testplan

B.9.18. ZkrH Hypervisor Entropy Register

Table 217. ZkrH Coverpoints

Google Sheet Testplan

B.9.19. SstcH Hypervisor Timer Compare

Table 218. SstcH Coverpoints

Google Sheet Testplan

B.9.20. SsstateenH Hypervisor State Enable

Table 219. SsstateenH Coverpoints

Google Sheet Testplan

B.9.21. SscrindH Hypervisor Indirect CSR Access

Hypervisor indirect CSR access.

Table 220. SscrindH Coverpoints

Google Sheet Testplan

B.9.22. SscfgH Hypervisor Counter Delegation

Table 221. SscfgH Coverpoints

Google Sheet Testplan

B.9.23. SmctrH Hypervisor Control Transfer Records

Table 222. SmctrH Coverpoints

Google Sheet Testplan

B.9.24. SvinvalH Hypervisor Memory Management Table Invalidation

Table 223. SvinvalH Coverpoints

Google Sheet Testplan

B.9.25. SvaduH Hypervisor Hardware Page Table A/D Updates

Table 224. SvaduH Coverpoints

Google Sheet Testplan

B.9.26. ZicfilpH Hypervisor Landing Pads

Table 225. ZicfilpH Coverpoints

Google Sheet Testplan

B.9.27. ZicfissH Hypervisor Shadow Stack

Table 226. ZicfissH Coverpoints

Google Sheet Testplan

B.9.28. SsdbltrpH Hypervisor Double Trap

Table 227. SsdbltrpH Coverpoints

Google Sheet Testplan

B.9.29. SsnpmH Hypervisor Pointer Masking

Table 228. SsnpmH Coverpoints

Google Sheet Testplan

B.9.30. SmnpmH Hypervisor Pointer Masking

Table 229. SmnpmH Coverpoints

Google Sheet Testplan

B.10. Miscellaneous RV23 Privileged Extensions

B.10.1. Sscofpmf Counter filtering

B.10.2. Ssstateen Supervisor State Enable

B.10.3. Ssu64xl 64-bit User Mode

Ssstateen Coverpoints

RV64 only

B.10.4. Sscounterenw Writable Counter Enables

B.10.5. Sstvecd Direct Trap Vector

B.10.6. Sstvala Trap Address

B.10.7. Ss1p13 Supervisor Mode 1.13

B.10.8. Ssnpm Pointer Masking

B.10.9. Smnpm Pointer Masking

B.10.10. Smmpm Pointer Masking

B.10.11. Zicfilp Landing Pads

Smmpm Coverpoints

In Privileged section because it has both unpriv and privileged behaviors.

B.10.12. Zicfiss Shadow Stack

Zicfilp Coverpoints

In Privileged section because it has both unpriv and privileged behaviors.

B.10.13. Zawrs Wait on Reservation Set

Zicfiss Coverpoints

Waits until timeout on a single hart that cannot modify the reservation set.

B.10.14. Sdtrig Debug Triggers

Zawrs Coverpoints

Located here because it is part of RVA23 and can function without the rest of the Debug Specification. See Section C.1 for non-RVA23 debug extensions.

Sdtrig Coverpoints

  • also check the value written to stval and vstval. Should be the VA of the breakpoint when Sstvala and Shvstvala are supported. This is automatically checked against the reference model, so there is no need for additional SdtrigSstvala and SdtrigShvstvala test suites.

B.11. Miscellaneous Non-RV23 Privileged Extensions

B.11.1. Sm1p13 Machine Mode 1.13

B.11.2. Smstateen Machine State Enable

B.11.3. Smcsrind Machine-Mode Indirect CSR Access

B.11.4. Sscsrind Supervisor-Mode Indirect CSR Access

B.11.5. Smepmp Enhanced PMP

B.11.6. Smrnmi Machine-Mode Resumable Non-Maskable Interrupts

B.11.7. Ssrnmi Supervisor-Mode Resumable Non-Maskable Interrupts

B.11.8. Smcntrpmf Counter Privilege Mode Filtering

B.11.9. Smcdeleg Counter Delegation

B.11.10. Ssccfg Counter Delegation

B.11.11. Smdbltrp Machine Double Traps

B.11.12. Ssdbltrp Supervisor Double Traps

B.11.13. Smctr Control Transfer Records

B.11.14. Ssqosid Quality-of-Service ID

Ssqosid Coverpoints

TODO: This text is here to prevent Asciidoctor from rendering strangely after an empty table. Delete it when table is populated.

Appendix C: Non-ISA Test Plan

This chapter contains test plans for ratified RISC-V standards outside the Unprivileged and Privileged ISA specifications.

C.1. Debug

This section describes ISA and non-ISA debug-related extensions not required in RVA23.

External debug needs to be able to perform register I/O to the debug module, such as halting and resuming the core, sending abstract commands such as Access Register or Access Memory, or running code from the Program Buffer. This cannot be done from software running on the core because a program cannot halt and single step itself, so these tests will need additional testbench support. External debug is not in RVA23 but may be added in a future phase.

A suggested approach is to require all of DM, DTM, and Sdext supported together for systems with External Debug, and to have a testbench send JTAG commands via DTM to the DTM to exercise Debug Mode.

C.1.1. DM Debug Module

C.1.2. DTM Debug Transport Module

C.1.3. Sdext Debug Extension

C.2. AIA Advanced Interrupt Architecture

This section describes AIA extension test plans.

C.2.1. Smaia Machine-Mode Advanced Interrupt Architecture

C.2.2. Ssaia Supervisor-Mode Advanced Interrupt Architecture

C.2.3. IMSIC Incoming MSI Controller

C.2.4. APLIC Advanced Platform-Level Interrupt Controller

C.3. I/O Memory Management Unit (IOMMU)

APLIC Coverpoints

This section describes IOMMU extension test plans.

C.3.1. IOMMU I/O Memory Management Unit

IOMMU Coverpoints

TODO: This text is here to prevent Asciidoctor from rendering strangely after an empty table. Delete it when table is populated.

Appendix D: UDB Parameters

Table 230 summarizes all of the UDB parameters that affect coverpoints in this testplan. Table 231 summarizes the UDB parameters that are not yet exercised.

Table 230. Used UDB Parameters
Parameter Dependent Coverpoints Defined By Description

ARCH_ID_VALUE

Sm_cg/cp_mcsr_access

Sm

The value of marchid The combination of mvendorid and marchid should uniquely identify the type of hart microarchitecture that is implemented.

COUNTINHIBIT_EN

Sm_cg/cp_inhibit

Sm

Indicates which hardware performance monitor counters can be disabled from mcountinhibit.

An unimplemented counter cannot be specified, i.e., if HPM_COUNTER_EN[3] is false, it would be illegal to set COUNTINHIBIT_EN[3] to true.

COUNTINHIBIT_EN[1] can never be true, since it corresponds to mcountinhibit.TM, which is always read-only-0.

IMP_ID_VALUE

Sm_cg/cp_mcsr_access

Sm

A unique encoding of the version of the processor implementation.

LRSC_FAIL_ON_NON_EXACT_LRSC

Zalrsc_cg/sc_d/cg_cp_custom_sc_lrsc, sc_w/cp_custom_sc_addresses

Zalrsc

Whether or not a Store Conditional fails if its physical address and size do not exactly match the physical address and size of the last Load Reserved in program order (independent of whether or not the SC is in the current reservation set)

LRSC_FAIL_ON_VA_SYNONYM

Zalrsc_cg/Not tested because spec does not require any specific behavior

Zalrsc

Whether or not an sc.l/sc.d will fail if its VA does not match the VA of the prior lr.l/lr.d, even if the physical address of the SC and LR are the same

LRSC_MISALIGNED_BEHAVIOR

ExceptionsZalrsc_cg/cp_{load,store}_address_misaligned

Zalrsc

What to do when an LR/SC address is misaligned and MISALIGNED_AMO == false.

* 'always raise misaligned exception': self-explainitory * 'always raise access fault': self-explainitory * 'custom': Custom behavior; misaligned LR/SC may sometimes raise a misaligned exception and sometimes raise a access fault. Will lead to an 'unpredictable' call on any misaligned LR/SC access

LRSC_RESERVATION_STRATEGY

Zalrsc_cg/sc_w/cp_custom_sc_addresses

Zalrsc

Strategy used to handle reservation sets.

* "reserve naturally-aligned 64-byte region": Always reserve the 64-byte block containing the LR/SC address * "reserve naturally-aligned 128-byte region": Always reserve the 128-byte block containing the LR/SC address * "reserve exactly enough to cover the access": Always reserve exactly the LR/SC access, and no more * "custom": Custom behavior, leading to an 'unpredictable' call on any LR/SC

MARCHID_IMPLEMENTED

Sm_cg/cp_mcsr_access

Sm

* false: marchid is not implemented, and must be read-only-0 * true: marchid is implemented, and the value is determined by ARCH_ID_VALUE

MIMPID_IMPLEMENTED

Sm_cg/cp_mcsr_access

Sm

* false: mimpid is not implemented, and must be read-only-0 * true: mimpid is implemented, and the value is determined by IMP_ID_VALUE

MISALIGNED_LDST

ExceptionsSm_cg/cp_{load_address_misaligned, store_address_misaligned, cp_misaligned_priority_load, cp_misaligned_priority_store}, Misalign_cg/cp_misalign

Sm

Does the implementation perform non-atomic misaligned loads and stores to main memory (does not affect misaligned support to device memory)? If not, the implementation always throws a misaligned exception.

MISALIGNED_LDST_EXCEPTION_PRIORITY

ExceptionsSm_cg/cp_misaligned_priority_load, cp_misaligned_priority_store

Sm

The relative priority of a load/store/AMO exception vs. load/store/AMO page-fault or access-fault exceptions.

May be one of:

[separator="!"] !=== ! low ! Misaligned load/store/AMO exceptions are always lower priority than load/store/AMO page-fault and access-fault exceptions. ! high ! Misaligned load/store/AMO exceptions are always higher priority than load/store/AMO page-fault and access-fault exceptions. !===

MISALIGNED_LDST_EXCEPTION_PRIORITY cannot be "high" when MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE is non-zero, since the atomicity of an access cannot be determined in that case until after address translation.

MISA_CSR_IMPLEMENTED

Sm_cg/cp_mcsr_access

Sm

Options:

true:: The misa CSR returns a non-zero value.

false:: The misa CSR is read-only-0.

MTVAL_WIDTH

ExceptionsSm_cg/TODO

Sm

The number of implemented bits in the mtval CSR. This is the CSR that may be written when a trap is taken into M-mode with exception-specific information to assist software in handling the trap (e.g., address associated with exception).

Must be greater than or equal to max(PHYS_ADDR_WIDTH, VA_SIZE)

MTVEC_ACCESS

ExceptionsSm_cg/all exception coverpoints, InterruptsSm_cg/all exception coverpoints

Sm

Options:

ro:: mtvec is read-only.

rw:: mtvec is read-write, but may not accept all values.

MTVEC_BASE_ALIGNMENT_DIRECT

ExceptionsSm_cg/all exception coverpoints, InterruptsSm_cg/all exception coverpoints

Sm

Minimum alignment of the base pointer. Because mtvec excludes the two least-significant bits of the base, the minimum alignment cannot be less than 4.

MTVEC_BASE_ALIGNMENT_VECTORED

InterruptsSm_cg/all

Sm

Because mtvec excludes the two least-significant bits of the base, the minimum alignment cannot be less than 4.

MTVEC_ILLEGAL_WRITE_BEHAVIOR

ExceptionsSm_cg/all exception coverpoints, InterruptsSm_cg/all

Sm

Options:

retain:: When either mtvec.MODE or mtvec.BASE is illegal, mtvec will retain its current value

custom:: When either mtvec.MODE or mtvec.BASE is illegal, mtvec will obtain an unpredictable value

Other values may be added over time once other common behaviors are identified.

MTVEC_MODES

InterruptsSm_cg/TODO

Sm

Options:

0:: Direct; All traps set pc to mtvec.BASE 1:: Vectored; Asynchronous interrupts set pc to mtvec.BASE + 4 x cause.

If only one mode is given, mtvec.MODE is assumed to be read-only with that value. Otherwise, mtvec.MODE is read-write.

MXLEN

Sm_cg/all tests

Sm

XLEN in machine mode, specified in bits

REPORT_ENCODING_IN_MTVAL_ON_ILLEGAL_INSTRUCTION

ExceptionsSm_cg/cp_illegal_instruction

Sm

Options:

* true: mtval is written with the encoding of an instruction causing an IllegalInstruction exception * false: mtval is written with 0 when an instruction causes an IllegalInstruction exception.

REPORT_VA_IN_MTVAL_ON_BREAKPOINT

ExceptionsSm_cg/cp_breakpoint

Sm

Options:

* true: mtval is written with the virtual PC of an EBREAK instruction (same information as mepc). * false: mtval is written with 0 on an EBREAK instruction.

Regardless, mtval is always written with a virtual PC when an external breakpoint is generated

REPORT_VA_IN_MTVAL_ON_INSTRUCTION_ACCESS_FAULT

ExceptionsSm_cg/cp_instr_access_fault

Sm

Options:

* true: mtval is written with the virtual address of a fetch causing the access fault * false: mtval is written with 0 when a fetch causes an access fault

REPORT_VA_IN_MTVAL_ON_INSTRUCTION_MISALIGNED

ExceptionsSm_cg/cp_instr_adr_misaligned_branch, cp_instr_misaligned_jal, cp_instr_misaligned_jalr

Sm

Options:

* true: mtval is written with the virtual address of a trapping misaligned fetch * false: mtval is written with 0 when a misaligned fetch traps

REPORT_VA_IN_MTVAL_ON_LOAD_ACCESS_FAULT

ExceptionsSm_cg/cp_load_access_fault

Sm

Options:

* true: mtval is written with the virtual address of a load causing the access fault * false: mtval is written with 0 when a load causes an access fault

REPORT_VA_IN_MTVAL_ON_LOAD_MISALIGNED

ExceptionsSm_cg/cp_load_address_misaligned

Sm

Options:

* true: mtval is written with the virtual address of a trapping misaligned load. * false: mtval is written with 0 when a misaligned load traps.

REPORT_VA_IN_MTVAL_ON_STORE_AMO_ACCESS_FAULT

ExceptionsSm_cg/cp_store_access_fault

Sm

Options:

* true: mtval is written with the virtual address of a store or AMO causing the access fault * false: mtval is written with 0 when a store or AMO causes an access fault

REPORT_VA_IN_MTVAL_ON_STORE_AMO_MISALIGNED

ExceptionsSm_cg/cp_store_address_misaligned

Sm

Options:

* true: mtval is written with the virtual address of a trapping misaligned store or AMO. * false: mtval is written with 0 when a misaligned store or AMO traps.

STVEC_MODE_DIRECT

InterruptsS_cg/TODO

S

Whether or not stvec.MODE supports Direct (0).

STVEC_MODE_VECTORED

InterruptsS_cg/TODO

S

Whether or not stvec.MODE supports Vectored (1).

TIME_CSR_IMPLEMENTED

Sm_cg/cp_mtime_write, Zicntr_cg/cp_cntr

Zicntr

Whether or not a real hardware time CSR exists. Implementations can either provide a real CSR or emulate access at M-mode.

Possible values:

true:: time/timeh exists, and accessing it will not cause an IllegalInstruction trap

false:: time/timeh does not exist. Accessing the CSR will cause an IllegalInstruction trap or enter an unpredictable state, depending on TRAP_ON_UNIMPLEMENTED_CSR. Privileged software may emulate the time CSR, or may pass the exception to a lower level.

TRAP_ON_EBREAK

ExceptionsSm_cg/cp_breakpoint

Sm

The spec states that implementations may handle EBREAKs transparently without raising a trap, in which case the EEI must provide a builtin.

TRAP_ON_ECALL_FROM_M

ExceptionsSm_cg/cp_ecall_m

Sm

The spec states that implementations may handle ECALLs transparently without raising a trap, in which case the EEI must provide a builtin.

VENDOR_ID_BANK

Sm_cg/cp_mcsr_access

Sm

Encodes the number of one-byte continuation codes in the Bank field of mvendorid.

iN JEDEC’s parlance, the bank number is one greater than the number of continuation codes; hence, the mvendorid Bank field encodes a value that is one less than the JEDEC bank number.

VENDOR_ID_OFFSET

Sm_cg/cp_mcsr_access

Sm

Encodes the final byte of a JEDEC manufactor ID, discarding the parity bit.
Table 231. Unused UDB Parameters
Parameter Defined By Description

ASID_WIDTH

S

Number of implemented ASID bits. Maximum is 16 for XLEN==64, and 9 for XLEN==32

CACHE_BLOCK_SIZE

Zicbom, Zicbop, Zicboz

The observable size of a cache block, in bytes

CONFIG_PTR_ADDRESS

Sm

The value returned from mconfigptr

DBG_HCONTEXT_WIDTH

Sdtrig

Specifies the size of HCONTEXT

DBG_SCONTEXT_WIDTH

Sdtrig

Specifies the size of SCONTEXT

DCSR_MPRVEN_TYPE

Sdtrig

Implementation of dcsr.MPRVEN is optional. It may be tied to either 0 or 1.

Behavior of the dcsr.MPRVEN bit: * 'read-only-0': tied to 0 * 'read-only-1': tied to 1 * 'rw': read-write

DCSR_STEPIE_TYPE

Sdtrig

Implementation of dcsr.STEPIE is optional. It may be tied to either 0 or 1.

Behavior of the dcsr.STEPIE bit: * 'read-only-0': tied to 0 * 'read-only-1': tied to 1 * 'rw': read-write

DCSR_STOPCOUNT_TYPE

Sdtrig

Implementation of dcsr.STOPCOUNT is optional. It may be tied to either 0 or 1.

Behavior of the dcsr.STOPCOUNT bit: * 'read-only-0': tied to 0 * 'read-only-1': tied to 1 * 'rw': read-write

DCSR_STOPTIME_TYPE

Sdtrig

Implementation of dcsr.STOPTIME is optional. It may be tied to either 0 or 1.

Behavior of the dcsr.STOPTIME bit: * 'read-only-0': tied to 0 * 'read-only-1': tied to 1 * 'rw': read-write

ELEN

Zvl32b

The maximum size in bits of a vector element that any operation can produce or consume.

FOLLOW_VTYPE_RESET_RECOMMENDATION

Zvl32b

It is recommended that at reset, vtype.vill is set, the remaining bits in vtype are zero, and vl is set to zero. If this parameter is set to true, this recommendation is followed. If it is false, at reset the respective fields will be UNDEFINED_LEGAL.

FORCE_UPGRADE_CBO_INVAL_TO_FLUSH

Zicbom

When true, an implementation prohibits setting menvcfg.CBIE == 11 such that all cbo.inval instructions either trap (when menvcfg.CBIE == '00') or flush (when menvcfg.CBIE == '01').

When false, an implementation allows a true INVAL operation for cbo.inval, and thus supports the setting menvcfg.CBIE == 11.

GSTAGE_MODE_BARE

H

Whether or not writing mode=Bare is supported in the hgatp register.

HCONTEXT_AVAILABLE

Sdtrig

Specifies if HCONTEXT is available

HCOUNTENABLE_EN

H

Indicates which counters can delegated via hcounteren

An unimplemented counter cannot be specified, i.e., if HPM_COUNTER_EN[3] is false, it would be illegal to set HCOUNTENABLE_EN[3] to true.

HCOUNTENABLE_EN[0:2] must all be false if Zicntr is not implemented. HCOUNTENABLE_EN[3:31] must all be false if Zihpm is not implemented.

HPM_COUNTER_EN

Smhpm

List of HPM counters that are enabled. There is one entry for each hpmcounter.

The first three entries must be false (as they correspond to CY, IR, TM in, e.g. mhmpcountinhibit) Index 3 in HPM_COUNTER_EN corresponds to hpmcounter3. Index 31 in HPM_COUNTER_EN corresponds to hpmcounter31.

HPM_EVENTS

Smhpm

List of defined event numbers that can be written into hpmeventN

HSTATEEN_AIA_TYPE

Ssaia, H, Ssstateen

Behavior of the hstateen0.AIA bit:

* 'rw': read-write * 'read-only-0': read-only, fixed to 0 * 'read-only-1': read-only, fixed to 1

HSTATEEN_CONTEXT_TYPE

Sdtrig, H, Ssstateen

Behavior of the hstateen0.CONTEXT bit:

* 'rw': read-write * 'read-only-0': read-only, fixed to 0 * 'read-only-1': read-only, fixed to 1

HSTATEEN_CSRIND_TYPE

Sscsrind, H, Ssstateen

Behavior of the hstateen0.CSRIND bit:

* 'rw': read-write * 'read-only-0': read-only, fixed to 0 * 'read-only-1': read-only, fixed to 1

HSTATEEN_ENVCFG_TYPE

H, Ssstateen

Behavior of the hstateen0.ENVCFG bit:

* 'rw': read-write * 'read-only-0': read-only, fixed to 0 * 'read-only-1': read-only, fixed to 1

HSTATEEN_IMSIC_TYPE

Ssaia, H, Ssstateen

Behavior of the hstateen0.IMSIC bit:

* 'rw': read-write * 'read-only-0': read-only, fixed to 0 * 'read-only-1': read-only, fixed to 1

HSTATEEN_JVT_TYPE

Zcmt, H, Ssstateen

Behavior of the hstateen0.JVT bit:

* 'rw': read-write * 'read-only-0': read-only, fixed to 0 * 'read-only-1': read-only, fixed to 1

HW_MSTATUS_FS_DIRTY_UPDATE

F, Sm

Indicates whether or not hardware will write to mstatus.FS

Values are: [separator="!"] !=== h! never ! Hardware never writes mstatus.FS h! precise ! Hardware writes mstatus.FS to the Dirty (3) state precisely when F registers are modified h! imprecise ! Hardware writes mstatus.FS imprecisely. This will result in a call to unpredictable() on any attempt to read mstatus or write FP state. !===

HW_MSTATUS_VS_DIRTY_UPDATE

Zvl32b, Sm

Indicates whether or not hardware will write to mstatus.VS

Values are: [separator="!"] !=== h! never ! Hardware never writes mstatus.VS h! precise ! Hardware writes mstatus.VS to the Dirty (3) state precisely when V registers are modified h! imprecise ! Hardware writes mstatus.VS imprecisely. This will result in a call to unpredictable() on any attempt to read mstatus or write vector state. !===

IGNORE_INVALID_VSATP_MODE_WRITES_WHEN_V_EQ_ZERO

H

Whether writes from M-mode, U-mode, or S-mode to vsatp with an illegal mode setting are ignored (as they are with satp), or if they are treated as WARL, leading to undpredictable behavior.

IMPRECISE_VECTOR_TRAP_SETTABLE

Zvl32b

Some profiles may provide a privileged configuration bit that selects between precise and imprecise vector trap behavior, allowing flexibility in how traps and partial updates are reported.

JVT_BASE_MASK

Zcmt

Mask representing the implemented bits of jvt.BASE. Includes the implicitly-zero bits of jvt.BASE, so JVT_BASE_MASK[5:0] must always be 0.

JVT_BASE_TYPE

Zcmt

Type of the jvt.BASE CSR field. One of:

* mask: jvt.BASE contains one or more implemented bits, which are indicated by JVT_BASE_MASK. * custom: Custom behavior. Will cause hart to enter 'unpredictable' state on a write to jvt.BASE.

JVT_READ_ONLY

Zcmt

If Zcmt is implemented, JVT is implemented, but can contain a read-only value

LEGAL_VSTART

Zvl32b

Implementations may raise illegal-instruction exceptions for vector instructions that specify a vstart value the implementation can never produce under the same vtype configuration (e.g., due to restrictions on supported strides or alignments).

MCID_WIDTH

Ssqosid

Number of bits used for the Monitoring Counter ID field (MCID). Default is 12.

MCONTEXT_AVAILABLE

Sdtrig

Specifies if MCONTEXT is available

MCOUNTENABLE_EN

U

Indicates which counters can be delegated via mcounteren.

An unimplemented counter cannot be specified, i.e., if HPM_COUNTER_EN[3] is false, it would be illegal to set MCOUNTENABLE_EN[3] to true.

MCOUNTENABLE_EN[0:2] must all be false if Zicntr is not implemented. MCOUNTENABLE_EN[3:31] must all be false if Zihpm is not implemented.

MISALIGNED_AMO

Zaamo

whether or not the implementation supports misaligned atomics in main memory

MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE

Sm

When MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE is 0, the hart cannot atomically perform a misaligned load/store/AMO. When a power of two, the hart can atomically load/store/AMO a misaligned access that is fully contained in a MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE-aligned region.

[NOTE] Even if the hart is capable of performing a misaligned load/store/AMO atomically, a misaligned exception may still occur if the access does not have the appropriate Misaligned Atomicity Granule PMA set.

MISALIGNED_SPLIT_STRATEGY

Sm

Options:

* sequential_bytes: The load/store appears to be broken into byte-sized accesses that processed sequentially from smallest address to largest address * custom: Something else. Will result in a call to unpredictable() in the execution

MSTATEEN_AIA_TYPE

Ssaia, Smstateen

Behavior of the mstateen0.AIA bit:

* 'rw': read-write * 'read-only-0': read-only, fixed to 0 * 'read-only-1': read-only, fixed to 1

MSTATEEN_CONTEXT_TYPE

Sdtrig, Smstateen

Behavior of the mstateen0.CONTEXT bit:

* 'rw': read-write * 'read-only-0': read-only, fixed to 0 * 'read-only-1': read-only, fixed to 1

MSTATEEN_CSRIND_TYPE

Sscsrind, Smstateen

Behavior of the mstateen0.CSRIND bit:

* 'rw': read-write * 'read-only-0': read-only, fixed to 0 * 'read-only-1': read-only, fixed to 1

MSTATEEN_ENVCFG_TYPE

S, Smstateen

Behavior of the mstateen0.ENVCFG bit:

* 'rw': read-write * 'read-only-0': read-only, fixed to 0 * 'read-only-1': read-only, fixed to 1

MSTATEEN_IMSIC_TYPE

Ssaia, Smstateen

Behavior of the mstateen0.IMSIC bit:

* 'rw': read-write * 'read-only-0': read-only, fixed to 0 * 'read-only-1': read-only, fixed to 1

MSTATEEN_JVT_TYPE

Zcmt, Smstateen

Behavior of the mstateen0.JVT bit:

* 'rw': read-write * 'read-only-0': read-only, fixed to 0 * 'read-only-1': read-only, fixed to 1

MSTATUS_FS_LEGAL_VALUES

Sm, F, S

The set of values that mstatus.FS supports.

MSTATUS_TVM_IMPLEMENTED

S

Whether or not mstatus.TVM is implemented.

When not implemented mstatus.TVM will be read-only-zero.

MSTATUS_VS_LEGAL_VALUES

Sm, Zvl32b, S

The set of values that mstatus.VS will accept from a software write.

MUTABLE_MISA_A

A, Sm

When the A extensions is supported, indicates whether or not the extension can be disabled in the misa.A bit.

MUTABLE_MISA_B

B, Sm

Indicates whether or not the B extension can be disabled with the misa.B bit.

MUTABLE_MISA_C

C, Sm

Indicates whether or not the C extension can be disabled with the misa.C bit.

MUTABLE_MISA_D

D, Sm

Indicates whether or not the D extension can be disabled with the misa.D bit.

MUTABLE_MISA_F

F, Sm

Indicates whether or not the F extension can be disabled with the misa.F bit.

MUTABLE_MISA_H

Sm, H

Indicates whether or not the H extension can be disabled with the misa.H bit.

MUTABLE_MISA_M

M, Sm

Indicates whether or not the M extension can be disabled with the misa.M bit.

MUTABLE_MISA_Q

Q, Sm

Indicates whether or not the Q extension can be disabled with the misa.Q bit.

MUTABLE_MISA_S

S, Sm

Indicates whether or not the S extension can be disabled with the misa.S bit.

MUTABLE_MISA_U

U, Sm

Indicates whether or not the U extension can be disabled with the misa.U bit.

MUTABLE_MISA_V

V, Sm

Indicates whether or not the V extension can be disabled with the misa.V bit.

M_MODE_ENDIANNESS

Sm

Options:

[separator="!"] !=== h! little ! M-mode data is always little endian h! big ! M-mode data is always big endian h! dynamic ! M-mode data can be either little or big endian, depending on the CSR field mstatus.MBE !===

NUM_EXTERNAL_GUEST_INTERRUPTS

H

Number of supported virtualized guest interrupts

Corresponds to the GEILEN parameter in the RVI specs

NUM_PMP_ENTRIES

Smpmp

Number of implemented PMP entries. Can be any value between 0-64, inclusive.

The architecture mandates that the number of implemented PMP registers must appear to be 0, 16, or 64.

Therefore, pmp registers will behave as follows according to NUN_PMP_ENTRIES:

[separator="!"] !=== ! NUM_PMP_ENTRIES ! pmpaddr<0-15> / pmpcfg<0-3> ! pmpaddr<16-63> / pmpcfg<4-15> ! 0 ! N ! N ! 1-16 ! Y ! N ! 17-64 ! Y ! Y !===

N = Not implemented; access will cause IllegalInstruction if TRAP_ON_UNIMPLEMENTED_CSR is true Y = Implemented; access will not cause an exception (from M-mode), but register may be read-only-zero if NUM_PMP_ENTRIES is less than the corresponding register

[NOTE] pmpcfgN for an odd N never exists when XLEN == 64

When NUM_PMP_ENTRIES is not exactly 0, 16, or 64, some extant pmp registers, and associated pmpNcfg, will be read-only zero (but will never cause an exception).

PHYS_ADDR_WIDTH

Sm

Implementation-defined size of the physical address space.

PMA_GRANULARITY

Sm

Generally, for systems with an MMU, should not be smaller than 12, as that would preclude caching PMA results in the TLB along with virtual memory translations

PMLEN

Smmpm, Smnpm, Ssnpm

The number of high-order bits of an address that are masked by the pointer masking facility.

PMP_GRANULARITY

Smpmp

log2 of the smallest supported PMP region.

Generally, for systems with an MMU, should not be smaller than 12, as that would preclude caching PMP results in the TLB along with virtual memory translations

Note that PMP_GRANULARITY is equal to G+2 (not G) as described in the privileged architecture.

PRECISE_SYNCHRONOUS_EXCEPTIONS

Sm

If false, any exception not otherwise mandated to precise (e.g., PMP violation) will cause execution to enter an unpredictable state.

RCID_WIDTH

Ssqosid

Number of bits used for the Resource Control ID field (RCID). Default is 12.

REPORT_CAUSE_IN_MTVAL_ON_LANDING_PAD_SOFTWARE_CHECK

Zicfilp

When true, mtval is written with the shadow stack cause (code=18) when a SoftwareCheck exception is raised into M-mode due to a landing pad error.

When false, mtval is written with 0.

REPORT_CAUSE_IN_MTVAL_ON_SHADOW_STACK_SOFTWARE_CHECK

Zicfiss

When true, mtval is written with the shadow stack cause (code=3) when a SoftwareCheck exception is raised into M-mode due to a shadow stack pop check instruction.

When false, mtval is written with 0.

REPORT_CAUSE_IN_STVAL_ON_LANDING_PAD_SOFTWARE_CHECK

Zicfilp

When true, stval is written with the shadow stack cause (code=18) when a SoftwareCheck exception is raised into S-mode due to a landing pad error.

When false, stval is written with 0.

REPORT_CAUSE_IN_STVAL_ON_SHADOW_STACK_SOFTWARE_CHECK

Zicfiss

When true, stval is written with the shadow stack cause (code=3) when a SoftwareCheck exception is raised into S-mode due to a shadow stack pop check instruction.

When false, stval is written with 0.

REPORT_CAUSE_IN_VSTVAL_ON_LANDING_PAD_SOFTWARE_CHECK

Zicfilp

When true, vstval is written with the shadow stack cause (code=18) when a SoftwareCheck exception is raised into VS-mode due to a landing pad error.

When false, vstval is written with 0.

REPORT_CAUSE_IN_VSTVAL_ON_SHADOW_STACK_SOFTWARE_CHECK

Zicfiss

When true, vstval is written with the shadow stack cause (code=3) when a SoftwareCheck exception is raised into VS-mode due to a shadow stack pop check instruction.

When false, vstval is written with 0.

REPORT_ENCODING_IN_STVAL_ON_ILLEGAL_INSTRUCTION

S

When true, stval is written with the encoding of an instruction that causes an IllegalInstruction exception.

When false stval is written with 0 when an IllegalInstruction exception occurs.

REPORT_ENCODING_IN_VSTVAL_ON_ILLEGAL_INSTRUCTION

H

When true, vstval is written with the encoding of an instruction that causes an IllegalInstruction exception.

When false vstval is written with 0 when an IllegalInstruction exception occurs.

REPORT_ENCODING_IN_VSTVAL_ON_VIRTUAL_INSTRUCTION

H

When true, vstval is written with the encoding of an instruction that causes an VirualInstruction exception.

When false vstval is written with 0 when an VirtualInstruction exception occurs.

REPORT_GPA_IN_HTVAL_ON_GUEST_PAGE_FAULT

H

When true, htval is written with the Guest Physical Address, shifted right by 2, that caused a GuestPageFault exception.

When false, htval is written with 0 when a GuestPageFault exception occurs.

REPORT_GPA_IN_TVAL_ON_INSTRUCTION_GUEST_PAGE_FAULT

H

Whether or not GPA >> 2 is written into htval/mtval2 when an instruction guest page fault occurs.

If false, 0 will be written into htval/mtval2 on an instruction guest page fault.

REPORT_GPA_IN_TVAL_ON_INTERMEDIATE_GUEST_PAGE_FAULT

H

Whether or not GPA >> 2 is written into htval/mtval2 when a guest page fault occurs while walking a VS-mode page table.

If false, 0 will be written into htval/mtval2 on an intermediate guest page fault.

REPORT_GPA_IN_TVAL_ON_LOAD_GUEST_PAGE_FAULT

H

Whether or not GPA >> 2 is written into htval/mtval2 when a load guest page fault occurs.

If false, 0 will be written into htval/mtval2 on a load guest page fault.

REPORT_GPA_IN_TVAL_ON_STORE_AMO_GUEST_PAGE_FAULT

H

Whether or not GPA >> 2 is written into htval/mtval2 when a store/amo guest page fault occurs.

If false, 0 will be written into htval/mtval2 on a store/amo guest page fault.

REPORT_VA_IN_MTVAL_ON_INSTRUCTION_PAGE_FAULT

S

When true, mtval is written with the virtual PC of an instructino when fetch causes an InstructionPageFault.

WHen false, mtval is written with 0 when an instruction fetch causes an InstructionPageFault.

REPORT_VA_IN_MTVAL_ON_LOAD_PAGE_FAULT

S

When true, mtval is written with the virtual address of a load when it causes a LoadPageFault.

WHen false, mtval is written with 0 when a load causes a LoadPageFault.

REPORT_VA_IN_MTVAL_ON_STORE_AMO_PAGE_FAULT

S

When true, mtval is written with the virtual address of a store when it causes a StoreAmoPageFault.

WHen false, mtval is written with 0 when a store causes a StoreAmoPageFault.

REPORT_VA_IN_STVAL_ON_BREAKPOINT

S

When true, stval is written with the virtual PC of the EBREAK instruction (same information as mepc).

When false, stval is written with 0 on an EBREAK instruction.

Regardless, stval is always written with a virtual PC when an external breakpoint is generated

REPORT_VA_IN_STVAL_ON_INSTRUCTION_ACCESS_FAULT

S

When true, stval is written with the virtual PC of an instructino when fetch causes an InstructionAccessFault.

WHen false, stval is written with 0 when an instruction fetch causes an InstructionAccessFault.

REPORT_VA_IN_STVAL_ON_INSTRUCTION_MISALIGNED

S

When true, stval is written with the virtual PC when an instruction fetch is misaligned.

When false, stval is written with 0 when an instruction fetch is misaligned.

Note that when IALIGN=16 (i.e., when the C or one of the Zc* extensions are implemented), it is impossible to generate a misaligned fetch, and so this parameter has no effect.

REPORT_VA_IN_STVAL_ON_INSTRUCTION_PAGE_FAULT

S

When true, stval is written with the virtual PC of an instructino when fetch causes an InstructionPageFault.

WHen false, stval is written with 0 when an instruction fetch causes an InstructionPageFault.

REPORT_VA_IN_STVAL_ON_LOAD_ACCESS_FAULT

S

When true, stval is written with the virtual address of a load when it causes a LoadAccessFault.

WHen false, stval is written with 0 when a load causes a LoadAccessFault.

REPORT_VA_IN_STVAL_ON_LOAD_MISALIGNED

S

When true, stval is written with the virtual address of a load instruction when the address is misaligned and MISALIGNED_LDST is false.

When false, stval is written with 0 when a load address is misaligned and MISALIGNED_LDST is false.

REPORT_VA_IN_STVAL_ON_LOAD_PAGE_FAULT

S

When true, stval is written with the virtual address of a load when it causes a LoadPageFault.

WHen false, stval is written with 0 when a load causes a LoadPageFault.

REPORT_VA_IN_STVAL_ON_STORE_AMO_ACCESS_FAULT

S

When true, stval is written with the virtual address of a store when it causes a StoreAmoAccessFault.

WHen false, stval is written with 0 when a store causes a StoreAmoAccessFault.

REPORT_VA_IN_STVAL_ON_STORE_AMO_MISALIGNED

S

When true, stval is written with the virtual address of a store instruction when the address is misaligned and MISALIGNED_LDST is false.

When false, stval is written with 0 when a store address is misaligned and MISALIGNED_LDST is false.

REPORT_VA_IN_STVAL_ON_STORE_AMO_PAGE_FAULT

S

When true, stval is written with the virtual address of a store when it causes a StoreAmoPageFault.

WHen false, stval is written with 0 when a store causes a StoreAmoPageFault.

REPORT_VA_IN_VSTVAL_ON_BREAKPOINT

H

When true, vstval is written with the virtual PC of the EBREAK instruction (same information as mepc).

When false, vstval is written with 0 on an EBREAK instruction.

Regardless, vstval is always written with a virtual PC when an external breakpoint is generated.

REPORT_VA_IN_VSTVAL_ON_INSTRUCTION_ACCESS_FAULT

H

When true, vstval is written with the virtual PC of an instructino when fetch causes an InstructionAccessFault.

WHen false, vstval is written with 0 when an instruction fetch causes an InstructionAccessFault.

REPORT_VA_IN_VSTVAL_ON_INSTRUCTION_MISALIGNED

H

When true, vstval is written with the virtual PC when an instruction fetch is misaligned.

When false, vstval is written with 0 when an instruction fetch is misaligned.

Note that when IALIGN=16 (i.e., when the C or one of the Zc* extensions are implemented), it is impossible to generate a misaligned fetch, and so this parameter has no effect.

REPORT_VA_IN_VSTVAL_ON_INSTRUCTION_PAGE_FAULT

H

When true, vstval is written with the virtual PC of an instructino when fetch causes an InstructionPageFault.

WHen false, vstval is written with 0 when an instruction fetch causes an InstructionPageFault.

REPORT_VA_IN_VSTVAL_ON_LOAD_ACCESS_FAULT

H

When true, vstval is written with the virtual address of a load when it causes a LoadAccessFault.

WHen false, vstval is written with 0 when a load causes a LoadAccessFault.

REPORT_VA_IN_VSTVAL_ON_LOAD_MISALIGNED

H

When true, vstval is written with the virtual address of a load instruction when the address is misaligned and MISALIGNED_LDST is false.

When false, vstval is written with 0 when a load address is misaligned and MISALIGNED_LDST is false.

REPORT_VA_IN_VSTVAL_ON_LOAD_PAGE_FAULT

H

When true, vstval is written with the virtual address of a load when it causes a LoadPageFault.

WHen false, vstval is written with 0 when a load causes a LoadPageFault.

REPORT_VA_IN_VSTVAL_ON_STORE_AMO_ACCESS_FAULT

H

When true, vstval is written with the virtual address of a store when it causes a StoreAmoAccessFault.

WHen false, vstval is written with 0 when a store causes a StoreAmoAccessFault.

REPORT_VA_IN_VSTVAL_ON_STORE_AMO_MISALIGNED

H

When true, vstval is written with the virtual address of a store instruction when the address is misaligned and MISALIGNED_LDST is false.

When false, vstval is written with 0 when a store address is misaligned and MISALIGNED_LDST is false.

REPORT_VA_IN_VSTVAL_ON_STORE_AMO_PAGE_FAULT

H

When true, vstval is written with the virtual address of a store when it causes a StoreAmoPageFault.

WHen false, vstval is written with 0 when a store causes a StoreAmoPageFault.

RESERVED_VSET_X0X0_VILL_SET

Zvl32b

When rs1 = x0 and rd = x0, vset instructions act as if the current vector length in vl is used as the AVL. If vill is set or the configuration is reserved, implementations may set vill to indicate unsupported use of these encodings.

RESERVED_VSET_X0X0_VLMAX_CHANGE

Zvl32b

When rs1=x0 and rd=x0, the instructions operate as if the current vector length in vl is used as the AVL. Use of the vset instructions with a new SEW/LMUL ratio that would result in a change of VLMAX is reserved. Implementations may set vill in either case.

RVV_VL_WHEN_AVL_LT_DOUBLE_VLMAX

Zvl32b

The value assigned to VL when AVL < 2*VLMAX.

SATP_MODE_BARE

S

Whether or not satp.MODE == Bare is supported.

SCOUNTENABLE_EN

S, Zicntr, Zihpm

Indicates which counters can delegated via scounteren

An unimplemented counter cannot be specified, i.e., if HPM_COUNTER_EN[3] is false, it would be illegal to set SCOUNTENABLE_EN[3] to true.

SCOUNTENABLE_EN[0:2] must all be false if Zicntr is not implemented. SCOUNTENABLE_EN[3:31] must all be false if Zihpm is not implemented.

SEW_MIN

Zvl32b

Implementations must provide fractional LMUL settings that allow the narrowest supported element width (SEW) to occupy a fractional portion of a vector register relative to the widest supported SEW. In general, implementations must support LMUL >= SEW_MIN/ELEN, where SEW_MIN is the narrowest supported SEW and ELEN is the widest SEW.

SSTATEEN_JVT_TYPE

Zcmt, Ssstateen

Behavior of the sstateen0.JVT bit:

* 'rw': read-write * 'read-only-0': read-only, fixed to 0 * 'read-only-1': read-only, fixed to 1

STVAL_WIDTH

S

The number of implemented bits in stval.

Must be greater than or equal to max(PHYS_ADDR_WIDTH, VA_SIZE)

SUPPORT_FRACTIONAL_LMUL_BEYOND_REQUIRED

Zvl32b

For a given supported fractional LMUL setting, implementations must provide support for SEW settings covering the range from SEW_MIN up to LMUL * ELEN, inclusive. This ensures types narrower than the maximum SEW are supported when fractional LMULs are selected.

SV32X4_TRANSLATION

H

Whether or not Sv32x4 translation mode is supported.

SV32_VSMODE_TRANSLATION

H

Whether or not Sv32 translation is supported in first-stage (VS-stage) translation.

SV39X4_TRANSLATION

H

Whether or not Sv39x4 translation mode is supported.

SV39_VSMODE_TRANSLATION

H

Whether or not Sv39 translation is supported in first-stage (VS-stage) translation.

SV48X4_TRANSLATION

H

Whether or not Sv48x4 translation mode is supported.

SV48_VSMODE_TRANSLATION

H

Whether or not Sv48 translation is supported in first-stage (VS-stage) translation.

SV57X4_TRANSLATION

H

Whether or not Sv57x4 translation mode is supported.

SV57_VSMODE_TRANSLATION

H

Whether or not Sv57 translation is supported in first-stage (VS-stage) translation.

SXLEN

S

Set of XLENs supported in S-mode. Can be one of:

* 32: SXLEN is always 32 * 64: SXLEN is always 64 * [32, 64]: SXLEN can be changed (via mstatus.SXL) between 32 and 64

S_MODE_ENDIANNESS

S

Endianness of data in S-mode. Can be one of:

* little: S-mode data is always little endian * big: S-mode data is always big endian * dynamic: S-mode data can be either little or big endian, depending on the CSR field mstatus.SBE

TINST_VALUE_ON_BREAKPOINT

H

Value written into htinst/mtinst on a Breakpoint exception from VU/VS-mode.

Possible values: * "always zero": Always write the value zero * "custom": Write a custom value, which results in UNPREDICTABLE

TINST_VALUE_ON_FINAL_INSTRUCTION_GUEST_PAGE_FAULT

H

Value to write into htval/mtval2 when there is a guest page fault on a final translation.

Possible values: * "always zero": Always write the value zero * "always pseudoinstruction": Always write the pseudoinstruction

TINST_VALUE_ON_FINAL_LOAD_GUEST_PAGE_FAULT

H

Value to write into htval/mtval2 when there is a guest page fault on a final translation.

Possible values: * "always zero": Always write the value zero * "always pseudoinstruction": Always write the pseudoinstruction * "always transformed standard instruction": Always write the transformation of the standard instruction encoding * "custom": A custom value, which will cause an UNPREDICTABLE event.

TINST_VALUE_ON_FINAL_STORE_AMO_GUEST_PAGE_FAULT

H

Value to write into htval/mtval2 when there is a guest page fault on a final translation.

Possible values: * "always zero": Always write the value zero * "always pseudoinstruction": Always write the pseudoinstruction * "always transformed standard instruction": Always write the transformation of the standard instruction encoding * "custom": A custom value, which will cause an UNPREDICTABLE event.

TINST_VALUE_ON_INSTRUCTION_ADDRESS_MISALIGNED

H

Value written into htinst/mtinst when there is an instruction address misaligned exception.

Possible values: * "always zero": Always write the value zero * "custom": Write a custom value, which results in UNPREDICTABLE

TINST_VALUE_ON_LOAD_ACCESS_FAULT

H

Value written into htinst/mtinst on an AccessFault exception from VU/VS-mode.

Possible values: * "always zero": Always write the value zero * "always transformed standard instruction": Always write a transformed standard instruction as defined by H * "custom": Write a custom value, which results in UNPREDICTABLE

TINST_VALUE_ON_LOAD_ADDRESS_MISALIGNED

H

Value written into htinst/mtinst on a VirtualInstruction exception from VU/VS-mode.

Possible values: * "always zero": Always write the value zero * "always transformed standard instruction": Always write a transformed standard instruction as defined by H * "custom": Write a custom value, which results in UNPREDICTABLE

TINST_VALUE_ON_LOAD_PAGE_FAULT

H

Value written into htinst/mtinst on a LoadPageFault exception from VU/VS-mode.

Possible values: * "always zero": Always write the value zero * "always transformed standard instruction": Always write a transformed standard instruction as defined by H * "custom": Write a custom value, which results in UNPREDICTABLE

TINST_VALUE_ON_MCALL

H

Value written into htinst/mtinst on a MCall exception from VU/VS-mode.

Possible values: * "always zero": Always write the value zero * "custom": Write a custom value, which results in UNPREDICTABLE

TINST_VALUE_ON_SCALL

H

Value written into htinst/mtinst on a SCall exception from VU/VS-mode.

Possible values: * "always zero": Always write the value zero * "custom": Write a custom value, which results in UNPREDICTABLE

TINST_VALUE_ON_STORE_AMO_ACCESS_FAULT

H

Value written into htinst/mtinst on an AccessFault exception from VU/VS-mode.

Possible values: * "always zero": Always write the value zero * "always transformed standard instruction": Always write a transformed standard instruction as defined by H * "custom": Write a custom value, which results in UNPREDICTABLE

TINST_VALUE_ON_STORE_AMO_ADDRESS_MISALIGNED

H

Value written into htinst/mtinst on a VirtualInstruction exception from VU/VS-mode.

Possible values: * "always zero": Always write the value zero * "always transformed standard instruction": Always write a transformed standard instruction as defined by H * "custom": Write a custom value, which results in UNPREDICTABLE

TINST_VALUE_ON_STORE_AMO_PAGE_FAULT

H

Value written into htinst/mtinst on a StoreAmoPageFault exception from VU/VS-mode.

Possible values: * "always zero": Always write the value zero * "always transformed standard instruction": Always write a transformed standard instruction as defined by H * "custom": Write a custom value, which results in UNPREDICTABLE

TINST_VALUE_ON_UCALL

H

Value written into htinst/mtinst on a UCall exception from VU/VS-mode.

Possible values: * "always zero": Always write the value zero * "custom": Write a custom value, which results in UNPREDICTABLE

TINST_VALUE_ON_VIRTUAL_INSTRUCTION

H

Value written into htinst/mtinst on a VirtualInstruction exception from VU/VS-mode.

Possible values: * "always zero": Always write the value zero * "custom": Write a custom value, which results in UNPREDICTABLE

TINST_VALUE_ON_VSCALL

H

Value written into htinst/mtinst on a VSCall exception from VU/VS-mode.

Possible values: * "always zero": Always write the value zero * "custom": Write a custom value, which results in UNPREDICTABLE

TRAP_ON_ECALL_FROM_S

S

Whether or not an ECALL-from-S-mode causes a synchronous exception.

The spec states that implementations may handle ECALLs transparently without raising a trap, in which case the EEI must provide a builtin.

TRAP_ON_ECALL_FROM_U

U

Whether or not an ECALL-from-U-mode causes a synchronous exception.

The spec states that implementations may handle ECALLs transparently without raising a trap, in which case the EEI must provide a builtin.

TRAP_ON_ECALL_FROM_VS

H

Whether or not an ECALL-from-VS-mode causes a synchronous exception.

The spec states that implementations may handle ECALLs transparently without raising a trap, in which case the EEI must provide a builtin.

TRAP_ON_ILLEGAL_WLRL

Sm

Options:

* true: Writing an illegal value to a WLRL CSR field will cause an IllegalInstruction exception. * false: Writing an illegal value to a WLRL CSR field causes unpredictable behavior.

TRAP_ON_RESERVED_INSTRUCTION

Sm

Options:

* true: Fetching an unimplemented and/or undefined instruction from the standard/reserved opcode space will cause an IllegalInstruction exception. * false: Fetching an unimplemented and/or undefined instruction from the standard/reserved opcose space causes unpredictable behavior.

TRAP_ON_RESERVED_INSTRUCTION may be false while TRAP_ON_UNIMPLEMENTED_INSTRUCTION is true when a custom instruction is implemented in the standard/reserved opcode space.

TRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY

S

For implementations that make satp.MODE read-only zero (always Bare, i.e., no virtual translation is implemented), attempts to execute an SFENCE.VMA instruction might raise an illegal-instruction exception.

TRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY indicates whether or not that exception occurs.

TRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY has no effect when some virtual translation mode is supported.

TRAP_ON_UNIMPLEMENTED_CSR

Sm

Options:

* true: Accessing an unimplemented CSR (via a Zicsr instruction) will cause an IllegalInstruction exception. * false: Accessing an unimplemented CSR (via a Zicsr instruction) will cause unpredictable behavior.

TRAP_ON_UNIMPLEMENTED_INSTRUCTION

Sm

Options:

* true: Fetching an unimplemented instruction will cause an IllegalInstruction exception. * false: Fetching an unimplemented instruction causes unpredictable behavior.

An unimplemented instruction is any instruction encoding that is not defined by the implementation. Custom instructions are considered implemented.

UXLEN

U

Set of XLENs supported in U-mode. When both 32 and 64 are supported, SXLEN can be changed, via mstatus.UXL, between 32 and 64.

U_MODE_ENDIANNESS

U

Endianness of data in U-mode. Can be one of:

* little: U-mode data is always little endian * big: U-mode data is always big endian * dynamic: U-mode data can be either little or big endian, depending on the CSR field mstatus.UBE

VECTOR_FF_NO_EXCEPTION_TRIM

Zvl32b

Implementations may process fewer than vl elements and reduce vl even when no exception occurs. However, if vstart == 0 and vl > 0, at least one element must be processed.

VECTOR_FF_SEG_EXCEPTION_PARTIAL_LOAD

Zvl32b

For fault-only-first segment loads, if an exception occurs partway through the zeroth segment, the trap is taken. If it occurs in a subsequent segment, vl may be reduced to the index of that segment. It is implementation-defined whether a partial subset of the segment is loaded before the trap.

VECTOR_FF_UPDATE_PAST_TRIM

Zvl32b

Fault-only-first (FF) load instructions may update active destination elements beyond the index that causes vector-length trimming, but not past the original vl. These spurious updates need not reflect the true memory contents; non-idempotent memory should only be accessed when the load is guaranteed not to be retried.

VECTOR_LOAD_PAST_TRAP

Zvl32b

Vector load instructions may overwrite active destination vector register group elements past the element index where a trap is reported; the behavior for elements beyond the trap index is implementation-defined.

VECTOR_LOAD_SEG_FF_OVERWRITE_ELEMENTS_AFTER_FAULT

Zvl32b

Fault-only-first segment load instructions may overwrite destination vector register group elements beyond the point where a trap is reported or where vl is trimmed; the exact values written may be implementation-defined.

VECTOR_LS_INDEX_MAX_EEW

Zvl32b

A profile may place an upper limit on the maximum supported index EEW used by vector load/store indexing. For example, some profiles may limit indexing to sizes no larger than XLEN or a fixed EEW value.

VECTOR_LS_MISALIGNED_LEGAL

Zvl32b

If an element accessed by a vector memory instruction is not naturally aligned to the size of the element, either the element is transferred successfully or an address misaligned exception is raised on that element. Support for misaligned vector memory accesses is independent of an implementation’s support for misaligned scalar memory accesses.

VECTOR_LS_SEG_PARTIAL_ACCESS

Zvl32b

If a trap occurs during access to a segment, it is implementation-defined whether some, all, or none of that segment’s element accesses are performed before the trap is taken.

VECTOR_LS_WHOLEREG_MISALIGNED_LEGAL

Zvl32b

Implementations may raise a misaligned address exception for whole-register loads/stores if the base address is not aligned to the maximum of the encoded EEW size (in bytes) or the implementation’s smallest supported SEW (in bytes).

VFREDUSUM_FINAL_NODE_ELEMENT_BEHAVIOR

Zvl32b

Implementations are permitted to insert an additional additive identity into the final reduction result, which may affect the final outcome when no active elements are present.

VFREDUSUM_INACTIVE_NODE_ELEMENT_BEHAVIOR

Zvl32b

A reduction node that receives an input derived solely from masked-off elements or elements beyond vl may either treat that input as the additive identity for the appropriate element width or copy the other input through unchanged to the node output.

VFREDUSUM_NAN

Zvl32b

The reduction tree structure must be deterministic for a given vtype and vl; as a consequence, implementations need not preserve NaN payloads when no elements are active. If no elements are active and the scalar input is NaN, implementations may canonicalize it (and raise an exception if it is a signaling NaN) or pass it through unchanged.

VFREDUSUM_NODE_ROUNDING_BEHAVIOR

Zvl32b

Each reduction operator computes an exact sum using an ideal scalar floating-point addition, then converts that result into a floating- point format with range and precision at least as large as the element SEW, rounding with the current dynamic rounding mode and raising exceptions as needed. Implementations may choose the exact range and precision per operator.

VILL_SET_ON_RESERVED_VTYPE

Zvl32b

Use of vtype encodings with LMUL < SEW_MIN/ELEN is reserved. Implementations may set the vill status bit to indicate such vtype encodings are unsupported, providing a software-visible indication of invalid vtype selections.

VLEN

Zvl32b

The number of bits in a single vector register.

VMID_WIDTH

H

Number of bits supported in hgatp.VMID (i.e., the supported width of a virtual machine ID).

VSSTAGE_MODE_BARE

H

Whether or not writing mode=Bare is supported in the vsatp register.

VSSTATUS_VS_EXISTS

Zvl32b

Some implementations provide a vsstatus.VS field even when the misa.V bit is clear. This parameter indicates whether vsstatus.VS exists independently of the misa.V setting.

VSTVEC_MODE_DIRECT

H

Whether or not vstvec.MODE supports Direct (0).

VSTVEC_MODE_VECTORED

H

Whether or not stvec.MODE supports Vectored (1).

VSXLEN

H

Set of XLENs supported in VS-mode. Can be one of:

* [32]: VSXLEN is always 32 * [64]: VSXLEN is always 64 * [32, 64]: VSXLEN can be changed (via hstatus.VSXL) between 32 and 64

VS_MODE_ENDIANNESS

H

Endianness of data in VS-mode. Can be one of:

* little: VS-mode data is always little endian * big: VS-mode data is always big endian * dynamic: VS-mode data can be either little or big endian, depending on the CSR field hstatus.VSBE

VUXLEN

H

Set of XLENs supported in VU-mode. When both 32 and 64 are supported, VUXLEN can be changed via vsstatus.UXL.

VU_MODE_ENDIANNESS

H

Endianness of data in VU-mode. Can be one of:

* little: VU-mode data is always little endian * big: VU-mode data is always big endian * dynamic: VU-mode data can be either little or big endian, depending on the CSR field vsstatus.UBE

Appendix E: Examples

This appendix gives examples of coverpoints and tests consistent with the test plan. These examples are not the only way to satisfy the testplan.

E.1. Unprivileged example: add

Coverage is in I_coverage.svh:

Listing 2. add Covergroup
covergroup I_add_cg with function sample(ins_t ins);
    option.per_instance = 0;
    cp_asm_count : coverpoint ins.ins_str == "add"  iff (ins.trap == 0 )  {
        //Number of times instruction is executed
        bins count[]  = {1};
    }
    cp_rs1 : coverpoint ins.get_gpr_reg(ins.current.rs1)  iff (ins.trap == 0 )  {
        //RS1 register assignment
    }
    cp_rs2 : coverpoint ins.get_gpr_reg(ins.current.rs2)  iff (ins.trap == 0 )  {
        //RS2 register assignment
    }
    cp_rd : coverpoint ins.get_gpr_reg(ins.current.rd)  iff (ins.trap == 0 )  {
        //RD register assignment
    }
    cp_rs1_edges : coverpoint unsigned'(ins.current.rs1_val)  iff (ins.trap == 0 )  {
        `ifdef XLEN32
            bins zero  =    {0};
            bins one  =     {32'b00000000000000000000000000000001};
            bins two  =     {32'b00000000000000000000000000000010};
            bins min  =     {32'b10000000000000000000000000000000};
            bins minp1  =   {32'b10000000000000000000000000000001};
            bins max  =     {32'b01111111111111111111111111111111};
            bins maxm1  =   {32'b01111111111111111111111111111110};
            bins ones  =    {32'b11111111111111111111111111111111};
            bins onesm1  =  {32'b11111111111111111111111111111110};
            bins walkeodd = {32'b10101010101010101010101010101010};
            bins walkeven = {32'b01010101010101010101010101010101};
            wildcard bins random = {32'b01???????????????????????????010};
        `else
            bins zero  = {0};
            bins one      = {64'b0000000000000000000000000000000000000000000000000000000000000001};
            bins two      = {64'b0000000000000000000000000000000000000000000000000000000000000010};
            bins min      = {64'b1000000000000000000000000000000000000000000000000000000000000000};
            bins minp1    = {64'b1000000000000000000000000000000000000000000000000000000000000001};
            bins Wmax     = {64'b0000000000000000000000000000000011111111111111111111111111111111};
            bins Wmaxm1   = {64'b0000000000000000000000000000000011111111111111111111111111111110};
            bins Wmaxp1   = {64'b0000000000000000000000000000000100000000000000000000000000000000};
            bins Wmaxp2   = {64'b0000000000000000000000000000000100000000000000000000000000000001};
            bins max      = {64'b0111111111111111111111111111111111111111111111111111111111111111};
            bins maxm1    = {64'b0111111111111111111111111111111111111111111111111111111111111110};
            bins ones     = {64'b1111111111111111111111111111111111111111111111111111111111111111};
            bins onesm1   = {64'b1111111111111111111111111111111111111111111111111111111111111110};
            bins walkeodd = {64'b1010101010101010101010101010101010101010101010101010101010101010};
            bins walkeven = {64'b0101010101010101010101010101010101010101010101010101010101010101};
            wildcard bins random = {64'b01???????????????????????????????????????????????????????????010};
        `endif
    }
    cp_rs2_edges : coverpoint unsigned'(ins.current.rs2_val)  iff (ins.trap == 0 )  {
        `ifdef XLEN32
            bins zero  =    {0};
 ...
        `else
            bins zero  = {0};
            ...
        `endif
    }
    cr_rs1_rs2_edges : cross cp_rs1_edges,cp_rs2_edges  iff (ins.trap == 0 )  {
        //Cross coverage of RS1 edges and RS2 edges
    }
    cmp_rs1_rs2 : coverpoint ins.get_gpr_reg(ins.current.rs1)  iff (ins.current.rs1 == ins.current.rs2 & ins.trap == 0 )  {
        //Compare assignments of all registers
    }
    cmp_rd_rs1 : coverpoint ins.get_gpr_reg(ins.current.rd)  iff (ins.current.rd == ins.current.rs1 & ins.trap == 0 )  {
        //Compare assignments of all registers
    }
    cmp_rd_rs2 : coverpoint ins.get_gpr_reg(ins.current.rd)  iff (ins.current.rd == ins.current.rs2 & ins.trap == 0 )  {
        //Compare assignments of all registers
    }
    cmp_rd_rs1_rs2 : coverpoint ins.get_gpr_reg(ins.current.rd)  iff (ins.current.rd == ins.current.rs1 & ins.current.rd == ins.current.rs2 & ins.trap == 0 )  {
        //Compare assignments of all registers
    }
    cp_gpr_hazard_rw : coverpoint check_gpr_hazards(ins.hart, ins.issue)  iff (ins.trap == 0 )  {
        //GPR Hazard
        bins hazards[]  = {NO_HAZARD, RAW_HAZARD, WAW_HAZARD, WAR_HAZARD};
    }
endgroup

Corresponding RV32 tests are in tests/rv32/I/I-add.S. Observe how the directed tests align with the coverpoints and bins. Register numbers and values are randomized unless they are swept by the coverpoint. The RVTEST_SIGUPD macro compares the result against an expected signature produced by a reference model. When register 0 is used, it is loaded with a random value, but hardwired to 0, so the reference model will show that it behaves as 0.

Listing 3. add Tests
# Testcase cp_rs1 (Test source rs1 = x0)
li x0, 0xb4e96718 # initialize rs1
li x24, 0xeaa512b3 # initialize rs2
add x25, x0, x24 # perform operation
RVTEST_SIGUPD(x3, x25)

# Testcase cp_rs1 (Test source rs1 = x1)
li x1, 0x81c4ef2a # initialize rs1
li x6, 0x917cfa69 # initialize rs2
add x7, x1, x6 # perform operation
RVTEST_SIGUPD(x3, x7)

...

# Testcase cp_rs1 (Test source rs1 = x31)
mv x21, x31 # switch signature pointer register to avoid conflict with test
li x31, 0x1508dd4e # initialize rs1
li x14, 0x830d07b0 # initialize rs2
add x11, x31, x14 # perform operation
RVTEST_SIGUPD(x21, x11)


# Testcase cp_rd (Test destination rd = x0)
li x19, 0x1d01c852 # initialize rs1
li x9, 0x1bfbf146 # initialize rs2
add x0, x19, x9 # perform operation
RVTEST_SIGUPD(x20, x0)

# Testcase cp_rd (Test destination rd = x1)
li x26, 0x1e3aafcf # initialize rs1
li x19, 0x986da37b # initialize rs2
add x1, x26, x19 # perform operation
RVTEST_SIGUPD(x20, x1)

...

# Testcase cr_rs1_rs2_edges (Test source rs1 = 0x0 rs2 = 0x0)
li x15, 0x00000000 # initialize rs1
li x5, 0x00000000 # initialize rs2
add x11, x15, x5 # perform operation
RVTEST_SIGUPD(x10, x11)

# Testcase cr_rs1_rs2_edges (Test source rs1 = 0x0 rs2 = 0x1)
li x1, 0x00000000 # initialize rs1
li x31, 0x00000001 # initialize rs2
add x20, x1, x31 # perform operation
RVTEST_SIGUPD(x10, x20)

# Testcase cr_rs1_rs2_edges (Test source rs1 = 0x0 rs2 = 0x2)
li x27, 0x00000000 # initialize rs1
li x3, 0x00000002 # initialize rs2
add x11, x27, x3 # perform operation
RVTEST_SIGUPD(x10, x11)

# Testcase cr_rs1_rs2_edges (Test source rs1 = 0x0 rs2 = 0x80000000)
li x8, 0x00000000 # initialize rs1
li x5, 0x80000000 # initialize rs2
add x16, x8, x5 # perform operation
RVTEST_SIGUPD(x10, x16)

E.2. Test case example: cr_rs1_rs2_edges bin with rs1 = 0x0, rs2 = 0x80000000

# Testcase cr_rs1_rs2_edges (Test source rs1 = 0x0 rs2 = 0x80000000)
li x8, 0x00000000 # initialize rs1 in randomly selected register
li x5, 0x80000000 # initialize rs2 in randomly selected register
add x16, x8, x5 # perform operation, write randomly selected destination register
# load expected value of 0x800000000 into x20 from table pointed to by x10. Check x20 against x16 and report mismatch
RVTEST_SIGUPD(x10, x16, x20)

RVTEST_SIGUPD macro:

if (RVTEST_SELFCHECK) # check result against signature
    LREG x20, 0(x10)
    beq x16, x20, 1f
    ecall
    1f:
else # generate signature
    SREG x16, 0(x10)
    addi x10, x10, WORDSIZE
    nop
1. Extended RVVI adds signals for virtual memory verification, including physical and virtual instruction and data addresses, and I/D TLB entries.
2. Portions of riscvISACOV that depend on proprietary Synopsys code such as a disassembler have been replaced with open-source equivalents
3. cp_asm_count is an exception, just counting the number of times the instruction was executed
4. Certain instructions are omitted if not supported for a given SEW. For example, widening add vwadd.vv is not supported for SEW=64, and vrgatherei16.v is not supported for SEW=8.